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#11
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by night_prowler - May 14, 2024, 05:03:10 PM
Hi John,

Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?

I have tried a separate 12V supply and get the same result.


Can you try out to formate SD with only one fat32 partition and try again?

I have tried this and get the same result.

Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?

I can see the following both with the SD Card installed and not.

IMG_3776.png
#12
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by night_prowler - May 14, 2024, 01:18:13 PM
Hi,

Thankyou for the reply.

Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
Well, interesting you should say that, the board has been wired to a Power Supply as in the image.  I can try with a normal 12V power supply and see if that works.

IMG_3775.png

You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.

Yes, I was at the point of trying anything  :)


Can you try out to formate SD with only one fat32 partition and try again?

I will try this as well after I have tried a different Power Supply.

Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?
At this moment in time I haven't been able to get the HW Manager to communicate with the board at all via the JTAG...  this might be my next question :-)

I will reply once more when I have tested the Power Supply and SD Card reformat, thankyou.
#13
CYC1000 community projects / Re: I present a comunity of IN...
Last post by Subcritical - May 14, 2024, 12:50:35 AM
Explanation of the errors produced in the UnAMIGA core implementation, which is why the CYC1000 is very interesting to have a PAL clock 28,37516Mhz to achieve an Amiga - Minimig hdl correct description. - Spanish -


PIN DESCRIPTION:
https://github.com/AtlasFPGA/PINOUT_ATLAS_CYC1000

We choose the CYC1000 because it has two clocks one With PIN_M2 a MENS 12Mhz an one free -> PAL 28,37516Mhz.

You can see some vídeos of the development UnAMIGA AGA CORE.

TURRICAN II AGA

NEW AMIGA OS

I have stopped being involved in the development of this UnAMIGA core but other ATLAS developers continue with its development.
#14
UltraScale / Re: TE0820-05-2AI21MA and TE07...
Last post by JH - May 13, 2024, 09:13:00 AM
Hi,
3 times blinking means board set to SD Boot, but did not finished booting:
https://wiki.trenz-electronic.de/display/PD/TE0820+CPLD#TE0820CPLD-LED

Can you tell me which power supply you use? Some current limit in case you use laboratory power supply?
You select barmetal Hello TE0820 Boot.bin, so Linux files are not needed in this case.
Can you try out to formate SD with only one fat32 partition and try again?
Can you also open one time Vivado HW manager and tell me if you see ARM_DAP and FPGA when you connect JTAG(one time without and one time with SD Card)?

br
John
#15
UltraScale / Re: TE0823-01-3PIU1MA Power Co...
Last post by JH - May 13, 2024, 08:58:59 AM
Hi, power consumption depends on your design and cooling solution. AMD offer some excel sheet and you can use vivado power planning (realistic environment parameter must be set). See also:
With our reference Design and TE0703 carrier board whole system takes appr. about 0,72A  @5V
br
John
#16
UltraScale / TE0820-05-2AI21MA and TE0701 (...
Last post by night_prowler - May 10, 2024, 03:45:46 PM
Hi,

 

I'm hoping someone can help me, I have the TE0820-05-2AI21MA MPSoC and a TE0701-05 Carrier Board.

 

I have been trying to boot the MPSoC from the prebuilt files within the "TE0820-test_board-vivado_2023.2-build_4_20240305102020" file that I downloaded from AMD.

 

Steps I have taken:

 

1) Prepare the SD Card with two Partitions, copied the following onto the FAT32 "boot" partition:

 

    test_board/prebuilt/os/petalinux/2GB/image.ub
    test_board/prebuilt/boot_images/2cg_1i_2gb/hello_te0820/boot.bif
    test_board/prebuilt/boot_images/2cg_1i_2gb/hello_te0820/BOOT.bin

2) I have the DIP switches set as per the image below.

3) Put the SD Card into the SD Slot and Powered Up

    My understanding here is that the SD Card being present puts the device into SD Boot Mode

 

When I do this, I just get the red LED's showing as per the below image and the Green LED flashes three times, then a gap and then three times again repeatedly.

Connecting to the Mini USB port and connecting via Putty I don't see any output.

If I take the SD Card out of the slot and repower, I get the same output as above. I suspect the device isn't booting from the SD Card at all.

Can anyone tell me that I am doing wrong?

Thankyou!
#17
UltraScale / TE0823-01-3PIU1MA Power Consum...
Last post by trongnghiavt3a - May 09, 2024, 10:42:12 AM
Hi,

We need some information about power consumption for TE0823-01-3PIU1MA module (MPSoC Module with AMD Zynq™ UltraScale+™ 3CG-L1I, 1 GByte LPDDR4, 4 x 5 cm), Can anyone help me?
#18
Trenz Electronic FPGA Modules / Re: Blinking LED on TE0715-05 ...
Last post by JH - May 08, 2024, 02:38:32 PM
Hi,
you want to change MIO7 (Zynq PS IO) --> Green LED1 (Designator D2)?

This is connected to PS MIO, please check this example:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841744/Gpio-PS+standalone+driver
--> https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/gpiops

MIO GPIO are activated on the reference design.
You can import this examples over Vitis Platform Board Support Package for standalone applications.

br
John




br
John
#19
Trenz Electronic FPGA Modules / Re: Memory write error at 0xF8...
Last post by JH - May 08, 2024, 01:35:54 PM
Hi,
can you check if you see ARM and FPGA device when you open Vivado HW manager?
Can you try to boot prebuilt Hello Trenz Boot.bin from SD Card?
br
John
#20
UltraScale / Re: Vitis Unified IDE 2023.2: ...
Last post by JH - May 08, 2024, 01:32:21 PM
Hi,
you are right, new IDE, doesn't work with our script and documentation. At the moment we use still Vitis classic for our designs.
br
John