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[64 Mbit (8 MB)]

#1

CYC1000 community projects / Re: Image sizes

Last post by tekskosong - October 08, 2026, 12:52:42 PM

The CYC1000 typically features a 64 Mbit (8 MB) SPI NOR flash (or 16 Mbit / 2 MB on older board revisions). The memory budget breaks down as follows:

[]

FPGA Configuration Bitstream (10CL025): Requires ~0.95 MB uncompressed. Enabling bitstream compression in Quartus reduces this footprint to roughly 350–500 KB.
[]Net Flash Available for Nios II Code:

[]

8 MB Board Revision: ~7.0 to 7.5 MB
[]2 MB Board Revision: ~1.0 to 1.5 MB
[/list]
[/list]

Execution Architecture: The SPI flash serves strictly as non-volatile storage. Upon boot, the bootloader copies the Nios II software image into the onboard 8 MB SDRAM (or internal M9K BRAM blocks) for runtime execution. This provides ample headroom for typical bare-metal C/C++ firmware or lightweight RTOS (e.g., FreeRTOS) deployments.

bead 16

teks kosong

[8 MB]

#2

CYC1000 community projects / Re: Image sizes

Last post by tekskosong - October 08, 2026, 12:48:00 PM

Depending on your CYC1000 board revision, the onboard SPI flash is either 8 MB or 2 MB:

[]

FPGA bitstream (10CL025): ~0.8 to 1 MB (or ~300–500 KB if compressed).
[]Available for Nios II SW: Roughly ~7 MB (on 8 MB flash) or ~1 to 1.2 MB (on 2 MB flash).
[/list]

At boot, the program typically uncompresses into the onboard 8 MB SDRAM to execute, so ~7 MB is more than enough for most Nios II applications.

#3

Trenz Electronic FPGA Modules / AXE5000 + CR00300 MIPI?

Last post by d.signer - October 08, 2026, 11:33:55 AM

Did anybody get the combination of AXE5000 + CR0300 + some MIPI camera (e.g. like any of the Raspberry Pi camera modules) working?

Or is there a reference design available somehwere? Presumably some simple RAW image capture using the MIPI PHY/CSI-RX only and not including all the qsys stuff for Altera VPP.

#4

Trenz Electronic FPGA Modules / Re: Problem with TEM0007 DDR s...

Last post by RC - September 30, 2026, 01:35:45 PM

Hello,

Please contact our support team support@trenz-electronic.de and provide the serial number and the article number of your TEM0007 module.

Best regards,
Ruoshui Chen

#5

Trenz Electronic FPGA Modules / Problem with TEM0007 DDR setti...

Last post by cone83 - September 30, 2026, 11:12:26 AM

I have a TEM0007 and I struggle with DDR problems. Running memtester on the booted linux system alone works fine, but when I run a design in the fabric that reads from DDR at a high band width and processes it, I get memory corruption. No data is actually written to DDR from the fabric.

Sometimes the system runs stable, sometimes it's very unstable. This seems to be random and depend on the boot (so I guess it depends on the DDR training run). Some DDR settings seemed to improve stability (but due to the randomness I'm not 100% sure). Those settings are:

* Enabling advanced CA trainig
* Setting ADD/CMD drive to 48

Are there any known DDR problems for this module? I have experimented with different timing parameters, but haven't found a combination that would work reliably.

Any help is welcome,
Thanks

#6

Trenz Electronic FPGA Modules / Boot image compatibility betwe...

Last post by blee - September 30, 2026, 02:44:09 AM

Hi.
I built a image file for AMB0010 Base with TE0955-01 SOM using TE0955-te0955-rd-vivado_2024.2-build_1_20250707150046.zip

Can I use that image file for TEB0955-02 Base with TE0955-01 SOM directly ?

Thanks a lot

[EN_LPD is 0]

#7

UltraScale / ps_aux on TE0817

Last post by benm - September 23, 2026, 12:55:59 PM

Hello,
I have a problem powering up a TE0817 module:
LP_DCDC is 3.3V
3.3VIN is 3.3V
EN_LPD is 0
LP_0V85 is 0 as expected
DCDC_2V0 is 0 as expected
PS_PLL is 0 as expected
but
PS_AUX is 0.47V
PS_1V8 is 0.86V
I don't understand how this is happens. I don't use PS_1V8 on my carrier board, it is just connected to a power plane but nothing else is there.
Do you have a hint on what is going on?
Thanks,
Ben

#8

Trenz Electronic FPGA Modules / Re: Request for BOM Informatio...

Last post by YakameinTakashi - September 18, 2026, 04:30:35 AM

Martin-san,

Thank you so much!

Kind regards,

Takashi

#9

Trenz Electronic FPGA Modules / Re: Request for BOM Informatio...

Last post by Martin R @Trenz - September 17, 2026, 04:03:02 PM

Hi,
please write a short message with your request to support@trenz-electronic.de

Best regards
Martin

#10

Trenz Electronic FPGA Modules / Re: TE0820-04: custom Vivado d...

Last post by MA - September 17, 2026, 02:46:24 PM

Hi,

since the original Trenz reference design works correctly on your TE0820/TE0706, the module and carrier board are basically working as expected.

For the custom design, however, we would need to see the actual hardware configuration and the changes made compared to the reference design to determine what is causing the issue.

Therefore, please contact our support team at support@trenz-electronic.de with the details of your custom hardware design, configuration, and boot log, if available. This will give us a better opportunity to investigate the cause of the issue and compare your design with the reference design.

Best regards,
Manuela