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1
Hi,
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Any idea why is this happening?
I don't know. Vitis is new, there are also other "small" bugs but I think Xilinx will fix this in the future.
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do you think that installing the patch might fix this?
is worth a try.

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By the way, when the fsbl is within the platform and it is compiled, where can I find the generated fsbl.elf file to use later to generate the petalinux image?
See my screeshot folder is: "export/Test(my platform name)/sw.../boot

Vitis will select this when you generate an application.
So after compiling platform project, add new application --> hello world , select the platform
Compile the project and select generate boot.bin. FSBL will be automatically selected, see my wiki documentation.
br
John
2
Hi,

(I'm using a VM running Ubuntu 18.04.1)

ok, I think I know whats the problem, I didn't generate the fsbl within the platform but as separate application instead (with "Generate boot components" not selected).

I followed the steps and added the sw_lib repository but when I'm creating the platform the zynqmp_fsbl is not adding the TE modified files (see attached) into the platform so I decided to compile the fsbl as a separate application and like that managed to create the fsbl.elf...

Any idea why is this happening? do you think that installing the patch might fix this?

By the way, when the fsbl is within the platform and it is compiled, where can I find the generated fsbl.elf file to use later to generate the petalinux image?

Thanks
 
3
Hi,
did you generate FSBL with the platform (with "Generate boot components" selected on the platform generation step ).
https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-CreateXSAwithVivado
On my place it works(see screenshot from the attachment):
I've generate a new workspace, add local repository and generate the platform (baremetal) with the same prebuilt XSA as you
-> can you send me one time the  reference zip file name which you has used

I use "Xilinx Vitis IDE v2019.2.1 (64-bit)
SW Build 2729669 on Thu Dec 5 04:49:55 MST 2019"

Can you install one time the patch for 2019.2.1 --> Use Xilinx information center, maybe this helps.

You use linux or? I use WinOS that's the second different between your and my place.
Which OS did you use exactly?

br
John


4
Hi John,

Thanks for your reply,

I'm not using our custom carrier,  I'm only working with the TEBF0808 + TE0803 (5EV) combination for the moment to make sure everything works with the 2019.2 version first.

I didn't modify/change anything at all, even I used the provided prebuild vivado xsa (StarterKit_5ev_i_4gb.xsa) from ".....\starterkit\prebuilt\hardware\5ev_i_4gb" folder and the fsbl TE modified sources found in "...starterkit\sw_lib" and I could not build the fsbl without disabling at least the FSBL_SECURE_EXCLUDE_VAL  feature
5
Hi,

starterkit reference design was generated with our template, so it should fit into the ocm.

Did you changed something --> enabled debug flags or modified something else?
I think you do, or? because wrote you want to use it on your own carrier.

I know enable debug flags and also disable compiler optimization together (for debugging) will not longer fit into OCM.

Some note: I've split Xilinx code and our specific one (files start with te* in the template). So you should better see which modification we have done. --> I've add "#TE MOD" comment to the xilinx code which I've modified to start our code.

br
John

br
John
6
Thank you for your prompt reply :).

I found that device support file was not installed.

I will install it and try again.

Many thanks.
7
I've found the answer to this here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/Zynq+UltraScale+FSBL as highlighted the problem is that the fsbl doesn't fit in the available OCM and reducing the footprint disabling some unused features , like changing FSBL_SECURE_EXCLUDE_VAL (in my case) solve the issue....
8
Hello,

I'm trying to rebuild the fsbl sources (TE modified) to create the fsbl.elf to later package the petalinux project image. (I need this step because I've also got to use a custom hardware carrier for the TE0803 SOM).

I'm using vitis 2019.2, I've downloaded the starter kit reference project files and I followed the steps here: https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-ZynqMP.1 to create a standalone application (based on the xda hw platform) and select the FSBL template (TE modified). Well the problem is that when I build the application I've got the next errors:

 
Code: [Select]
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: zynqmp_fsbl.elf section `.bss' will not fit in region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: address 0xfffee1f8 of zynqmp_fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: address 0xfffee1f8 of zynqmp_fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: address 0xfffee1f8 of zynqmp_fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: address 0xfffee1f8 of zynqmp_fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: address 0xfffee1f8 of zynqmp_fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: section .handoff_params VMA [00000000fffe9e00,00000000fffe9e87] overlaps section .bss VMA [00000000fffe7d40,00000000fffea0ff]
.../opt/Xilinx/Vitis/2019.2/gnu/aarch64/lin/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld: region `psu_ocm_ram_0_S_AXI_BASEADDR' overflowed by 17656 bytes

Any ideas what I'm doing wrong?

Thanks in advance.
9
Hi,
did you install the device support file for the MAX 10 FPGA?

br
Thomas
10
Hi,

I have downloaded "TEI0001-test_board-quartus_19.1.0-20200707153205.zip" and executed "create_project_win.cmd".
I selected TEI0001-02-08-C8 and pushed "Create project" button.
But I got some error messages as follows.

Info: Adding uart [altera_avalon_uart 19.1]
Info: Parameterizing module uart
Info: Building connections
Info: Parameterizing connections
Info: Validating
Info: Done reading input file
Error: NIOS_test_board.onchip_flash: Must assign a valid Device for Altera Onchip Flash megafunction.
Error: [TE_DES-30] Script (TE::QUART::generate_qsys) failed:
Error: [TE_TK-11] (TE) Script (TE::DES::run_project) failed: .


My Quatus environment is as follows.

Quaturs Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
Nios 2 software build Tool for Eclipse Version: Mars.2 Release (4.5.2) Build id: 20160218-0600

What is necessary to create project?

Thank you.
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