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1
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by JH on August 22, 2019, 03:00:33 PM »
Hi,
you must use Boot.bin as programming file and fsbl to initialise zynqMP to programm QSPI. --> so both

Change Boot Mode to JTAG and use also the FSBL, which is used for boot.bin  or use the special FSBL for QSPI programming (in case boot mode is not JTAG) which is provided in our reference designs (also the source code as template.)
Reason for special FSBL in other modes:
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264#Vivado/SDK/SDSoC-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues
https://www.xilinx.com/support/answers/70148.html
https://www.xilinx.com/support/answers/70548.html

br
John
2
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by johnabel on August 22, 2019, 02:27:55 PM »
up to #6 it's all clear to me. #7 is the problem

I could write the qspi from the hardware manager, but it asks for a config file (that I assume it must contain an FSBL) and the FSBL in another box. That boots from QSPI, the FSBL prints a message, but doesn't jump to the App (bare metal in this case) and I'm not sure if it loads the PL.

SDK has the 'program flash' button that also asks for both boot image and FSBL. Should the boot image not have FSBL?
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Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by JH on August 22, 2019, 01:14:44 PM »
Hi,
"That doesn't apply much to me, I'm working on windows" --> SDK is available for Win OS.

Linux is only needed in case you want to generate a petalinux project. We do this part in a separate VM for our project for other parts we use also windows.

In case of Barmetal App, use Xilinx design flow.
1. Generate your Vivado design (include PS IP with your settings --> start with our reference design or board part files for your assembly variant)
2. Generate generate this design --> generate bitstream
3. Export HDF from your Vivado Project to SDK
4. generate FSBL with SDK (in case you use our starterkit and the corresponding PS setup, please use our FSBL template --> see reference design documentation)
5. (optional if needed depends on your running app) generate PMU firmware with SDK. --> not needed for simple hello world
6. Generate Boot.bin with SDK --> Include FSBL, Bitstream, App (this is automatically set when you generate before the FSBL and the Hello World app)
7. Use this Boot.bin and boot from SDK or configure QSPI Flash and boot from QSPI

br
John
4
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by johnabel on August 22, 2019, 10:49:51 AM »
That doesn't apply much to me, I'm working on windows

UG1137 is clarifying my doubts... I thought PL and PS were automatically (by the PMU) configured, but it looks like, with Zynq, the PMU just configures the PS and loads any software for it. It's the FSBL who configures the PL.
5
UltraScale / Re: TE0803 + TEBF0808, WRONG Polarity on FMC
« Last post by JH on August 21, 2019, 04:34:29 PM »
Hi,
polarity is swapped sometimes for better signal routing. Correct polarity is this one of the symbol pin name of the SoC. You can change polarity easy in your design.

For CLK polarity is in the most cases no matter.
But you need CLK input Pin to get CLK directly into the CLK routing resources of the SoC:
https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf
Xilinx U+ Zynq Pin definition, see:
https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf
or
https://www.xilinx.com/support/documentation/user_guides/ug1075-zynq-ultrascale-pkg-pinout.pdf


Route CLK over fabric into CLK routing resources of the SoC is also possible, but in this case tools has problems to calculate timings . It's not recommended and in case you still do it you must set some constrain attribute to allow vivado to do this otherwise you get an error. See Xilinx documentation.

br
John
6
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by JH on August 21, 2019, 04:18:48 PM »
Hi,
use SDK to generate Boot.bin

PS: Xilinx forum:
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/create-mcs-for-ZC706/td-p/699338
--->solution is a link to
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium
got to chapter --> https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium#PrepareBootMedium-QSPIBoot
first point: Tools Required --> Xilinx SDK

So use SDK to generate Boot.bin. This works fine.


br
John
7
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by johnabel on August 21, 2019, 02:18:46 PM »
I initially selected MCS format, trying BIN produces the same error.
This is something that Vivado does, it doesn't depend on what I attach to create the config file, I'd assume.

The project was created based on the TE0808 board file and anyways the target device is indeed a zynq Ultrascale+ that supports that mode, so I don't understand why the message pops up. Maybe a question for Xilinx instead...
8
CYC1000 community projects / Re: TEI0003-02-test_board-quartus_18.1-20190402.zip
« Last post by gawrcool on August 21, 2019, 10:48:26 AM »
Hi,
My fault. With a fresh install of the example and with modifying the path for the given hex file, it works.
The problem is the Platform Designer that doesn't tell you (no warning nor info message) that the mem_init initialization file is missing.
I use Quartus 18.1.0 on Ubuntu 18.04.
Regards,
Olivier
9
Trenz Electronic FPGA Modules / Re: what configuration interface for TE08XX?
« Last post by JH on August 21, 2019, 09:37:26 AM »
Hi,
Flash is connected as dual parallel. This is also configured in our reference designs and board part files.

Use sdk and *.bin format.
You must also include fsbl and in case of linux also pmu and atf firmware.
See reference design. Definition file (open the bif file with SDK bitgen gui or text editor) for bin is include in the prebuilt folder:
  • prebuilt\boot_images\<assembly version>\u-boot
  • \prebuilt\boot_images\<assembly version>\hello_te0808

br
John
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CYC1000 community projects / Re: TEI0003-02-test_board-quartus_18.1-20190402.zip
« Last post by t.dueck on August 21, 2019, 09:35:32 AM »
Hi,
we actually work on a solution, where the correct path will be set automatically.
At the moment you have to set the correct path for the *.hex file manually. See step 2 - 5 in the link below:
- https://wiki.trenz-electronic.de/display/PD/TEI0003+Test+Board#TEI0003TestBoard-DesignFlow
I have tried the .hex file in the zip file again and it works.
- did you use win os or linux os?
- which quartus version did you use?
- which step from the design flow (link above) failed?
br
thomas

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