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Trenz Electronic FPGA Modules / Re: Design a 4-core processor on FPGA
« Last post by JH on December 14, 2018, 11:13:26 AM »
Hello,
Quote
How feasible it is to design a 4-core cpu on a FPGA Spartan 3E.
Why would you want to to this?

Quote
At my school
Student? You should switch to newer FPGA Technology. --> 7 Series from Xilinx and Vivado.

To CAN:
 7 Series  or UltraScale+ Zynq has CAN interface included into PS. Connectable to MIO or EMIO, that's the easiest way to have CAN on  FPGA.

Can HDL IP from Xilinx(not free):
Xilinx CAN driver:
Some open Source (I din't checked content):

br
John
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Trenz Electronic FPGA Modules / Design a 4-core processor on FPGA
« Last post by kymyc on December 12, 2018, 04:02:02 PM »
Hello,

How feasible it is to design a 4-core cpu on a FPGA Spartan 3E. I don't want to design something complicated, but a processor to test a few algorithms, designed for embedded, how fast they can run on[url] FPGA[https://pcbworld.hqew.net/Rigid-PCB/product-detail/1234705]...

And there is another question.At my school we were given this 3 months project, which consists on doing the design and implementation of our own CAN (Controller Area Network) IP (Intellectual Property) with FPGA, then adding the IP to 2 SoPCs (Software on Programmable Chip). And then establishing communication through CAN between the 2 SoPCs.
After several resarches, we found out that we can't implement all the functionalities, and that if we are to make our own IP, it will be implementing the major functionalities only.
And that all is about understanding how a CAN Controller and a CAN Transceiver work.

I am asking for links or advice, that will help us filter the maor functonalities and implement the IP correctly.

Thanks in advance.

Thank you.
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Trenz Electronic FPGA Modules / Re: TE0720 Pull-up voltage for system-controller pins
« Last post by AndyH on December 10, 2018, 04:12:22 PM »
Thanks!
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Trenz Electronic FPGA Modules / Re: TE0720 Pull-up voltage for system-controller pins
« Last post by JH on December 10, 2018, 10:54:24 AM »
Hello,
this is refereed to FPGA IOs, see also Xilinx documentation:For JTAG, you should use JM2-91(JTAG VREF). In case of TE0720 it's the same like 3.3VIN, but we have also other 4x5 modules where it is connected directly to Xilinx FPGA and internal 3.3V is used.
Use the 3.3V or 1.8V output of the module to enable your power regulators of the FPGA IOs.   

So if the B2B IO is connected to 3.3VIN, you can pullup with 3.3VIN, if it's connected to internal  module voltage(3.3 or 1.8), you should use this one or your carrier voltage, which is enabled with 3.3V or 1.8V out.

We have some general notes to 4x5 power supply, controller IOs and general pinout:br
John
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Trenz Electronic FPGA Modules / SCSoC Platfrom Package for TE0726 Zynqberry
« Last post by zb_fan on December 08, 2018, 03:01:19 PM »
Hi,

Did anybody manage to build a Zynqberry SCSoC Platform package for 2017.2 or later? The format seems to have changed from the 2016.2 (and earlier) platform package format which is available from the te0726_m_sdsoc reference design.

I am trying to port XAPP1300 (Very good paper on a Lucas-Kanade Optical Flow SCSoC implementation!) to the zynqberry. Unfortunately it doesn't fit to the xc7z010 device with 2016.2. With 2017.2 it fits with the available microzed platform (which has a xc7z010 too). It needs 98.5% of the Slices, 55% of the Block RAMs and 90% of the DSPs  :)
But most of it is overhead for the FIFOs and interconnects and I am ultimately trying to integrate it into the zynqberry demo project to make it switchable between viedo pass-through and real time dense optical flow output.

Thanks & Regards,
Thomas
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Trenz Electronic FPGA Modules / TE0720 Pull-up voltage for system-controller pins
« Last post by AndyH on December 07, 2018, 09:52:39 PM »
Hello,

We are designing a custom carrier board for the TE0720, and I wanted to clear up what seems like an ambiguity in the TRM (https://wiki.trenz-electronic.de/display/PD/TE0720+TRM). It says:

Quote
It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

Does that apply to any of the carrier board I/Os that go to the system controller rather than to the Zynq? I'm specifically concerned with MODE, RESIN, and the three JTAG inputs (TDI, TCK, and TMS). I want to have pull-ups for all of these on the carrier board, but I have to choose between pulling them to (a) 3.3VIN, which we generate on the carrier board or (b) 3.3V, which comes BACK from the carrier board when the Zynq is powered up. (a) means the signal will be asserted earlier in the startup process, before the Zynq has power.

My instinct is that these signals should be pulled to 3.3VIN, because they go to a bank of the system controller (CPLD) that is powered by 3.3VIN.
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UltraScale / Re: USB3 camera interface project. SOM and base board questions
« Last post by JH on December 07, 2018, 01:45:23 PM »
Hi,

ok fine, so short answer at the end: I think idea itself should be work with TE0803 and TEBF0808, but I did not check performance (most of them depends on the configuration and third party software/driver...).

br
John
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UltraScale / Re: USB3 camera interface project. SOM and base board questions
« Last post by joseer on December 07, 2018, 12:44:28 PM »
Hi John,

Yes, but in case the standard petalinux interface for USB vision doesn't work, instead start from scratch, I guess the drivers provided by the manufactures can be a good reference to develop the ones for arm. I'm not expecting to have a plug and play system, but at least I'd like to check if with this hardware this project can be achieved.

Many thanks for the hints and info.
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UltraScale / Re: USB3 camera interface project. SOM and base board questions
« Last post by JH on December 07, 2018, 12:24:36 PM »
Hi,
Quote
also the manufacturer provides linux drivers...so in principle, it shouldn't be a big issue to work with the stream, it has to be tested though.
Only a hint: linux is not always linux and this is on ARM processor with configurable periphery. It depends also what Xilinx and your camera manufacturer has implemented....

Quote
you mention that a SATA hard disk would be possible (with TEBF0808), can this be a SSD?
Normally yes.  But like hint above, it depends also on xilinx kernel/driver version. For example use SATA for rootfs does not work with vivado/petalinux 2017.1 but I heard it works with 18.1 and newer --> we plan to create the demo design with debian desktop filesystem on SATA harddisk/SSD.

I don't want to scare you right now, I would only inform you that maybe spend a little bit more time to get everything running.


br
John
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UltraScale / Re: USB3 camera interface project. SOM and base board questions
« Last post by joseer on December 07, 2018, 12:02:30 PM »
Hello JH,

Thanks for the reply and info.

The camera implements a standard USB3 Vision interface (https://www.ximea.com/en/usb3-vision-camera/usb3zone), also the manufacturer provides linux drivers...so in principle, it shouldn't be a big issue to work with the stream, it has to be tested though.

Also the camera provides high speed fps so it can be between 150-1000fps depending of the resolution, (being a low VGA resolution for the fastest). So I think at the end will be matter of mange the bandwidth, you mention that a SATA hard disk would be possible (with TEBF0808), can this be a SSD?
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