Recent Posts

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1
Trenz Electronic FPGA Modules / TE0720 soft reboot issue
« Last post by DG on May 23, 2020, 10:02:09 AM »
Hi,

I am using the TE020 in my application. The aim is, to load a new image in the QSPI flash and start it at run-time.


Therefore I would need to know the purpose of the BOOT_R and BOOT_R5 in the schematics: SCH-TE0720-03-1CR which are connected to the system controller CPLD.
Are these signals inputs to the CPLD, or could they have an impact if a QSPI boot is started at run-time?

Kind regards,
DG
2
Trenz Electronic FPGA Modules / TE0701 REV06 CPLD firmware fix
« Last post by arachek on May 22, 2020, 12:24:53 PM »
CPLD firmware (SC-PRJ-TE701-06_CC701-05_20161122) for TE0701 REV06 contain error on line 395:

Code: [Select]
LED1 <= vadj_led when rgpio_active='0' else rgpio_out(1);
This leads to that the LED1 works together with the LED2, when controlled via RGPIO.
To fix this, line 395 should be replaced with:

Code: [Select]
LED1 <= vadj_led when rgpio_active='0' else rgpio_out(0);
It will be nice, if Trenz add this fix to the new CPLD firmware version for TE0701.
3
Trenz Electronic FPGA Modules / TE0821 Carrier Design
« Last post by Francesco_Saitec on May 22, 2020, 12:01:47 PM »
Hello everyone,
I have to develop a carrier board for use with TE0821 SoM. I'm currently decide which supplies i need to. I take as reference design the TEF1002 carrier which provide 5V, 3V3 and 1V8 supplies to the module.
- Is it possible to supply the module with only 3V3 and 1V8 supplies? The EN6363QI mounted on SoM accept Vin from 2.7V to 6.6V.
- What is the power sequencing implemented by the MAX10 on TEF1002? I don't want to use a CPLD on my design so I want to recreate the sequencing made by the MAX10 via hardware.

Thanks in advance.
4
I am using Vitis to build a platform using the tes-board_1cf_1gb.xsa platform file. I am also created a Linux domain and using the prebuilt binaries from the trenz site.  I used the linux.bif binary and boot_linux directory for the TE07-03-1CFA.

I have created a basic hello world application that uses the platform I created above. I application builds without any errors.

Lastly, I have created boot.bin file:
/arch = zynq; split = false; format = BIN
the_ROM_image:
{
   [bootloader]C:\Users\xxx\workspace6\CNUPlatform\export\CNUPlatform\sw\CNUPlatform\boot\fsbl.elf
   C:\Users\xxx\workspace6\CNUPlatform\hw\test_board_1cf_1gb.bit
   C:\Users\xxx\Documents\test_board\prebuilt\os\petalinux\1GB\u-boot.elf
   C:\Users\xxx\workspace6\CNU\Debug\CNU.elf
}

I build the BOOT.bin file and copy the: BOOT. bin, fsbl.elf, and linux.bif in the boot directory to the SD card.

Output of Serial Port:
Xilinx First Stage Boot Loader (TE modified)

Release 2019.2   May 20 2020-10:56:26

I does not appears this is working correctly since I am expecting to see "Hello Word".   Can I use the pre-built binaries? Must I build the binaries for the OS using the Petalinx SDK?  I have noticed that on your web page there a note: "working in process .... coming soon" about this process. I would appreciate any suggestions you may have.  :)
5
Trenz Electronic FPGA Modules / Re: Can't Boot Hello World on TE0720
« Last post by jlanza on May 20, 2020, 08:02:27 PM »
I did mean test_board_1cf_1gb.xsa NOT test_board_1cf_1gb_io_report.xdc. I tried rebuilding the project again with one of your templates and included the Generic FAT File system and it worked as expected.  I am not sure if the Generic FAT File system was need?
6
SMF2000 community projects / SmartBerry DDR RAM trouble
« Last post by Aiy on May 19, 2020, 08:23:55 PM »
Hello,
I am working on porting Emcraft U-Boot and uClinux to the SmartBerry.
I am having trouble with reading and writing the DDR RAM.
To troubleshoot I use the provided Smartberry_Webserver SoftConsole Demo to test the RAM.
The following code is put in main.c to send a simple string to RAM and read it back, but I only get garbage and the debugger reports that the readback buffer "buf2" is mostly garbage, I see some characters are correctly aligned but most is just scrap.

Code: [Select]
char buf[64];
char buf2[64];
memset(buf, 0, 64);
memset(buf2, 0, 64);
#define CONFIG_SYS_RAM_BASE 0xA0000000
uint32_t *extmem = (uint32_t*)CONFIG_SYS_RAM_BASE;
uint8_t val;
for(val=0; val<10; val++){
sprintf(buf, "%d Dead men tell no tales.", val);
memcpy(extmem, buf, 64);
memcpy(buf2, extmem, 64);
printf("Local: %s From DRAM: %s\r\n", buf, buf2);
}

best regards
7
Trenz Electronic FPGA Modules / Schematics License and Loyalty Fees
« Last post by htala on May 18, 2020, 05:44:35 PM »
Dear Sir/Madam

Is there any document which explains about license usage of schematics provided by Trenz Electronics for company products?
There are many schematics on your website on different products of yours, like FPGA modules and evaluation boards, but there is no document for legal issues.

In particular, I want to copy a part of schematics of one your boards and almost completely customize it for my project (I'm an individual not an company and it's
just a hobby project for now but maybe in far-future it turns into an awesome product).

What should I do?
8
Trenz Electronic FPGA Modules / Re: PCIe Link down
« Last post by JH on May 18, 2020, 12:22:58 PM »
Hi,
you use the same vivado and petalinux on the TE0803 project like with MYIR Project?
--> when you compare, you should also use the same version. This make it maybe easier to find the different.

br
John




9
Trenz Electronic FPGA Modules / Re: PCIe Link down
« Last post by johnabel on May 18, 2020, 10:20:36 AM »
The Myir linux was built from scratch from the hardware specification. No need to fiddle with the device tree or other exotic stuff, just tweak the kernel and rootfs config. It's worth comparing, I'll do that when back to it.
10
Trenz Electronic FPGA Modules / Re: PCIe Link down
« Last post by JH on May 18, 2020, 08:55:42 AM »
Hi,
how did you generate linux for myir board?
Compare  setup (kernel config, rootfs config...) from both boards to find the different.
br
John
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