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1
UltraScale / FSBL for TE0820
« Last post by jhane on Today at 01:42:51 AM »
Hello,
   I have a question about the FSBL's in the release.  I understand that one is special version for flashing an empty flash.   However, what is the second one for?  I see it has support for i2c and the clock chip.    Is this just so ethernet will work?   We do not have ethernet on our custom carrier and the FSBL generated from the xsa seems to work fine.
   Is there anything in the modified FSBL that I should be patching my generated FSBL with?

thanks,
jeff
2
UltraScale / Re: TE0807 StarterKit with SO image
« Last post by gergarciaa on October 22, 2020, 05:41:21 PM »
MT and John thanks a lot for your repply!
It helped me a lot!!

cheers you both!
Ger
3
UltraScale / Re: TE0803 + 4EG // Timing constraints
« Last post by JH on October 19, 2020, 12:35:04 PM »
Hi,
Quote
So If I remove vio_general and RGPIO I still have all the functionality of the board ( display port, usb, ehternet, SFP, sata, can)
yes but there are also changes on Linux and FSBL need to bringing up all these  interfaces, see:
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit

br
John
4
UltraScale / Re: Paticularity of FMC_VADJ
« Last post by JH on October 19, 2020, 12:32:34 PM »
Hi,
Quote
Do you know what is the difference between the 2?
You mean between AXI I2C IP and PS I2C over PL? Both are from Xilinx:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
https://www.xilinx.com/products/intellectual-property/axi_iic.html

Either there is a misconfiguration of the AXI-I2C IP or you has a timing issue or some driver problems.

br
John
5
UltraScale / Re: Paticularity of FMC_VADJ
« Last post by SaW on October 19, 2020, 09:13:46 AM »
Hi,
we manage to make it work in the end, it was a mistake on our side.
We are using the LSF0108 from texas instruments, it is a level translator made for Open-Drain and push-pull applications. We added a pullup for the output and defined the pin in the implementation design (in vivado) with pullup as well.
What i meant was that by normal fonctionnement of the translator, a small current is sent back to the voltage reference A, which, in our case, is FMC_VADJ. I was wondering is this one support it. (but i guess it does since it is working now)

Another question i have, which is not really directed to FMC_VADJ but more to custom I2C. We tried first to assign it using the xilinx IP axi-iic and the driver associated. I can send data and interact with our camera via the i2c port once linux booted, but if i trie to load the camera driver there is some issue in the communication: I should read an eeprom(using the i2c we defined previously), and it reads the 10 first registers then  tells it is not possible anymore.
I then changed to use the I2C present in the PS and redifine the in/out ports. this time the driver worked, I could read all of the register from the eeprom
Do you know what is the differnece between the 2?

thank you a lot for your help
best regards,
Sarah
6
UltraScale / Re: TE0803 + 4EG // Timing constraints
« Last post by mt-user-2019 on October 19, 2020, 09:11:58 AM »
Hello John,

Thx for you answer.

So If I remove vio_general and RGPIO I still have all the functionality of the board ( display port, usb, ehternet, SFP, sata, can)
I have little pain to see the usage of RGPIO if it is me who can control it via vivado.

BR
MT
7
UltraScale / Re: Paticularity of FMC_VADJ
« Last post by JH on October 19, 2020, 07:26:48 AM »
Hi,
which kind of level translator did you use on your FMC-card? I2C need pullup resistors and some bidirectional level translator has problems with external pullups.


Quote
In the documentation of the voltage translator it is written that at normal application of the transaltor (VrefB > VrefA) a current will sync into VrefA, so into FMC_VADJ.
Is this possible? I couldnt find anything about this subject in the TRM or on the schematic.
I'm sorry I didn't understand this question.

br
John
8
UltraScale / Re: TE0807 StarterKit with SO image
« Last post by JH on October 19, 2020, 07:19:43 AM »
Hi MT,
thanks for your answers.

I have only a small addition to your second answer: It's not the Hello World app itself which initialised the PS-PL CLKs, it's the generated FSBL, which is also included into the Boot.bin. And in case you start Hello World with Vitis Debugger, it's a generated Xilinx script which initialise PS with setup from XSA file like the FSBL does (but in this case only Xilinx default without our FSBL changes).

br
John
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UltraScale / Re: TE0803 + 4EG // Timing constraints
« Last post by JH on October 19, 2020, 07:12:03 AM »
Hi,
theoretical you can remove all IPs, it depends on things you want to do ;-)

At the moment you has only removed audio. A little bit strange is that you get timing issues now, because I've run it on my place without timing issues.
Your timing issues comes from the VIO debug core which is connected the logic of the GPIO core, in this case I think you can ignore it. VIO can be controlled via Vivado HW Manager,so that signal changes when you change signal status on GUI can be considered more or less as static.

RGPIO is only a simple interface to the CPLD, where you can control/read some signal: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD#TEBF0808CPLD-RGPIO

You can remove the RGPIO hierarchy, when you didn't used it. You can also remove VIO for LED control. In case you did not use DP and CAN, you can also remove the SC0808 IP (or you set DP Loc constrain in your own XDC instead to use SC0808).

br
John
10
UltraScale / Re: TE0807 StarterKit with SO image
« Last post by mt-user-2019 on October 18, 2020, 04:10:38 PM »
Hi GERGARCIAA,

I am not working for trenz and I am still beginner but

Quote
in order to use the base board (TEBF0808) is it mandatory to use a linux OS image or can i create a Standalone image?
No it is not mandatory to have linux you can have standalone (BareMetal), freeRTOS (or other but it is not available with xilinx tools AFAIK) running on A53 Or/And R5.


Quote
I am actually not interested in using the PS at all so would it be possible to use the PL alone and still communicate with the baseboard and therefore not creating any image whatsoever?
Not 100% sure but if your clock come from the PS side you should wake up A53_0 and configure the clock. I would do at least : A53 standalone (BareMetal) with Hello world.

So the flow will be
Vivado : do the fpga side (what ever you want)
Vivado : export the xsa
Vitis : import xsa (create or update platform)
vitis : create the application Hello world

Run your hello world

Now you PS is awake with some ps -> pl clock
you can go back to vivado and play with it and reprogram the pl as long as you do not modify your clock 

BR
MT
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