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1
UltraScale / Re: make two ethernet ports work with TE820
« Last post by BNT on Today at 12:40:19 PM »
Hallo Oleksandr,

thanks for your answer.

“At MDIO address 5 you have GMII to RGMII core, not PHY.” => ok, I corrected reg = <5> to <0>
“You should put here an address and if possible driver settings for your real physical PHY” =>
I am not sure what Linux compatible to use for the TI DP83822
And I am not sure if the Phy requires other settings in the DT.

I tried following deviceTree-Settings:

 /* Ethernet 0 */
&gem0 {
    phy-handle = <&phy0>;
    status = "okay";
    phy-mode = "rgmii-id";
    phy0: ethernet-phy@0 {
         compatible = "marvell,88e1510";
         device_type = "ethernet-phy";   
         reg = <0>;
     };
};   

   Result: Terminaloutput while booting:
Cannot find device "eth1"
Cannot find device "eth1:1"
Cannot find device "eth1:1"

Second try:
/* Ethernet 0 */
&gem0 {
   status = "okay";
   phy-mode = "rgmii-id";
   ethernet_phy0: ethernet-phy@0 {
       compatible = "xlnx,xps-ethernetlite-1.00.a";
       device_type = "ethernet-phy";   
       reg = <0>;
    };

   Result:
Both ethernets can be recognized. Still pinging Ethernet 1 is not possible.

Third try: Removing compatible
/* Ethernet 0 */
&gem0 {
 status = "okay";
 phy-mode = "rgmii-id";
 ethernet_phy0: ethernet-phy@0 {
  //compatible = "xlnx,xps-ethernetlite-1.00.a";
  device_type = "ethernet-phy";   
  reg = <0>;
 };

   Result:
Cannot find device "eth1"
Cannot find device "eth1:1"
Cannot find device "eth1:1"


Still I am not able to run both Ethernets.

My questions:
1.)   What is the correct compatible for TI DP83822 Phy? Or exists a compatible list, where I can check?
2.)   Is there any need to mention MDIO in the devicetree?
3.)   Is there any need to mention rgmii-convertion in the devicetree?

4.)   At the moment I am changing devicetree, compiling and booting Linux to check what my changes effected. This workflow is very time-consuming: Is there any possibility to test changes in the devicetree without rebuilding Linuximage?

5.)   Is there any need to use petalinux 2018.3? At moment I am using

Linux PetaLinux 4.14.0-xilinx-v2018.2 #1 SMP Mon Dec 9 13:09:18 CET 2019 aarch64 aarch64 aarch64 GNU/Linux

Thanks a lot!

Kind Regards
Thomas

2
UltraScale / Re: SFP+ using TEBF08008 and TE0808
« Last post by JH on Today at 10:47:39 AM »
Hi,

Quote
I used the reference clock from the board --> B230_CLK0_P, B230_CLK0_N (I checked it from the schematic of TE0808 - page 11) --> It is driven from Si5345A chip.
If the Si5345A chip is not programmed by default --> Is there a procedure for programming it without FSBL?


SI Clock Builder Pro Software and Clock Builder Pro Field Programmer , see also:
https://wiki.trenz-electronic.de/display/PD/Si5345

--> I2C bus access for external programmer is connector marked as "D" in:
https://wiki.trenz-electronic.de/display/PD/TEBF0808+Getting+Started#TEBF0808GettingStarted-Overview

br
John
3
UltraScale / Re: SFP+ using TEBF08008 and TE0808
« Last post by hossam84 on Today at 10:32:19 AM »
Thanks for your reply.

did you use passive copper cable or optical cable? --> if optical check supported frequencies.
I am using Passive copper Cable Assembly from Molex (https://www.digikey.com/products/en?keywords=74752-2301)

Did you check that the MGTs REF clock is configured an valid? Which Reference CLK did you use? SI on the carrier is not programmed by default this is done temporary only with our modified FSBL in the reference design. --> it can also happens that you need other reference frequency like we default provide with the reference design
Maybe it's only a problem of Xilinx barmetal app, they run seldom out of the box.



I used the reference clock from the board --> B230_CLK0_P, B230_CLK0_N (I checked it from the schematic of TE0808 - page 11) --> It is driven from Si5345A chip.
If the Si5345A chip is not programmed by default --> Is there a procedure for programming it without FSBL?


What you can do to at first is to test MGT over SFP: Create Xilinx IBERT core for both SFP with your target frequency and loop back  to the second SFP port on the TEBF0808.
I will do your suggestion and get back to you if there is any issue.

Thanks,
H. H.
4
UltraScale / Re: SFP+ using TEBF08008 and TE0808
« Last post by JH on Today at 09:25:13 AM »
Hello,
did you use passive copper cable or optical cable? --> if optical check supported frequencies.
Did you check that the MGTs REF clock is configured an valid? Which Reference CLK did you use? SI on the carrier is not programmed by default this is done temporary only with our modified FSBL in the reference design. --> it can also happens that you need other reference frequency like we default provide with the reference design
Maybe it's only a problem of Xilinx barmetal app, they run seldom out of the box.

What you can do to at first is to test MGT over SFP: Create Xilinx IBERT core for both SFP with your target frequency and loop back  to the second SFP port on the TEBF0808.
br
John


5
UltraScale / Re: make two ethernet ports work with TE820
« Last post by Oleksandr Kiyenko on Today at 08:18:27 AM »
Hallo Thomas,

in your configuration you put
&gem0 {
    status = "okay";
   phy-mode = "rgmii-id";
   ethernet_phy5: ethernet-phy@5 {
              device_type = "ethernet-phy";
       compatible = "xlnx,xps-ethernetlite-1.00.a";
        reg = <5>;
    };
};
but it's wrong. At MDIO address 5 you have GMII to RGMII core, not PHY. You should put here an address and if possible driver settings for your real physical PHY.
GMII to RGMII core does not replace your PHY it just provides clock and signals interface conversion.
You can enable GMII to RGMII driver in your kernel settings or set fixed link speed for GMII to RGMII


BR
Oleksandr
6
UltraScale / SFP+ using TEBF08008 and TE0808
« Last post by hossam84 on Today at 07:14:17 AM »
Hello,

I am trying to use the SFP+ port of the TEBF08008 base board using the TE0808 board. I checked the datasheets and schematic of both board and I think I configured the pins accordingly.
I used the GEM0 for the purpose of SFP+ connection. IO used EMIO for the GEM0 (shown in the attachment) and then connected the GMII_ENET0 to gmii_gem_pcs_pma of the 1G/2.5G Ethernet PCS/PMA or SGMII IP. Also, I connected the MDIO_ENET0 to the mdio_pcs_pma of the 1G/2.5G Ethernet PCS/PMA or SGMII IP (shown in the attachment).
For the differential clock of the GT, I used the differential clock of the board as show in the schematic. I used SFP+ of MGT Lane 2 (B230_RX2_P, B230_RX2_N, B230_TX2_P, B230_TX2_N).

I configured the 1G/2.5G Ethernet PCS/PMA or SGMII IP same as the example of Xilinx application note xapp1306 - ps_emio_eth_1g.

After generating bit stream I export the hardware to run the SDK with lwip echo server example. I tried to make any connection with host which has the next-562sfp-10g module but I didn't get anything.

Is there anyone who has tested the SFP(+) who can provide me with some hints or guidlines.

Thanks in advance
7
UltraScale / make two ethernet ports work with TE820
« Last post by BNT on December 10, 2019, 12:58:40 PM »
Hallo to everybody,

I have a problem using two ethernet ports with te820 and I hope I will find help here.

First of all some information:
-   I am using Xilinx TE820 SoM from Trenz (TE0820-2EG-1EA)
-   Ethernet 1 uses the GEM3 and it is connected via MIO Pins to the PHY. It works fine with following DT:

* Ethernet 1 */
/* ETH PHY */
&gem3 {
    status = "okay";
    ethernet_phy1: ethernet-phy@1 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
        reg = <1>;
    };
};

-   Ethernet 0 uses the GEM0 and it is connected via EMIO Pins to the FPGA. There it goes to a gmii2rgmii converter and then to Ethernet Phy TI83822.
-   The gmii2rgmii has the following configuration:
see re-customizeIP.PNG in the attachments

-   The DT for Ethernet 0 looks like this:

/* Ethernet 0 */
&gem0 {
    status = "okay";
   phy-mode = "rgmii-id";
   ethernet_phy5: ethernet-phy@5 {
              device_type = "ethernet-phy";
       compatible = "xlnx,xps-ethernetlite-1.00.a";
        reg = <5>;
    };
};


While Booting I get following information on terminal:

Net:   ZYNQ GEM: ff0b0000, phyaddr ffffffff, interface rgmii-id
eth0: ethernet@ff0b0000ZYNQ GEM: ff0e0000, phyaddr ffffffff, interface rgmii-id
, eth1: ethernet@ff0e0000


[…]

[    1.405783] macb ff0b0000.ethernet: Not enabling partial store and forward
[    1.406222] libphy: MACB_mii_bus: probed
[    1.480625] macb ff0b0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 30 (80:1f:12:3a:ab:bd)
[    1.480646] TI DP83822 10/100 Mbps PHY ff0b0000.ethernet-ffffffff:01: attached PHY driver [TI DP83822 10/100 Mbps PHY] (mii_bus:phy_addr=ff0b000                                                                       0.ethernet-ffffffff:01, irq=POLL)
[    1.480978] macb ff0e0000.ethernet: Not enabling partial store and forward
[    1.481404] libphy: MACB_mii_bus: probed
[    1.481422] [Firmware Warn]: /amba/ethernet@ff0e0000/ethernet-phy@1: Whitelisted compatible string. Please remove
[    1.552710] macb ff0e0000.ethernet eth1: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 31 (80:1f:12:3a:ab:bd)
[    1.552726] Marvell 88E1510 ff0e0000.ethernet-ffffffff:01: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:01                                                                       , irq=POLL)

[…]
Configuring network interfaces... [    4.560977] pps pps0: new PPS source ptp0
[    4.564968] macb ff0b0000.ethernet: gem-ptp-timer ptp clock registered.
[    4.571571] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc (v1.24.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
[   13.779216] pps pps1: new PPS source ptp1
[   13.783172] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[   13.789811] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
udhcpc (v1.24.1) started
Sending discover...
Sending discover...
[   16.908741] macb ff0e0000.ethernet eth1: link up (1000/Full)
[   16.914344] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
Sending discover...
No lease, forking to background
done.


After Booting, using ifconfig, I get the information:

root@PetaLinux:~# ifconfig
eth0      Link encap:Ethernet  HWaddr 80:1F:12:3A:AB:BD
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)
          Interrupt:30

eth0:0    Link encap:Ethernet  HWaddr 80:1F:12:3A:AB:BD
          inet addr:10.0.0.2  Bcast:0.0.0.0  Mask:255.255.255.0
          UP BROADCAST MULTICAST  MTU:1500  Metric:1
          Interrupt:30

eth1      Link encap:Ethernet  HWaddr 80:1F:12:3A:AB:BD
          inet6 addr: fe80::821f:12ff:fe3a:abbd%4882584/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:65 errors:0 dropped:0 overruns:0 frame:0
          TX packets:51 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:7498 (7.3 KiB)  TX bytes:13230 (12.9 KiB)
          Interrupt:31

eth1:1    Link encap:Ethernet  HWaddr 80:1F:12:3A:AB:BD
          inet addr:10.0.1.2  Bcast:0.0.0.0  Mask:255.255.255.0
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          Interrupt:31

lo        Link encap:Local Loopback
          inet addr:127.0.0.1  Mask:255.0.0.0
          inet6 addr: ::1%4882584/128 Scope:Host
          UP LOOPBACK RUNNING  MTU:65536  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:0 (0.0 B)


 
Connecting / disconnecting my pc to Ethernet 0 and 1 shows terminal output:

[ 1821.196784] macb ff0e0000.ethernet eth1: link up (1000/Full)
[ 1824.268708] macb ff0e0000.ethernet eth1: link down
[ 1828.300755] macb ff0b0000.ethernet eth0: link up (100/Full)
[ 1830.348681] macb ff0b0000.ethernet eth0: link down


Seems somehow to be working… but: I can only ping Ethernet1.

I did check:
- IP Adress of my computer
- Firewall of my computer
- several compatibles in DeviceTree for &gem0
 (compatible = "marvell,88e1510";
  compatible = "ethernet-phy-id2000.5C90";
  compatible = "xlnx,xps-ethernetlite-1.00.a"

without getting ethernet0 to work.
   
Any hints what am I doing wrong?

Kind Regards
Thomas



8
UltraScale / Re: TE0820+TE0706,running Linux and FreeRTOS parallel
« Last post by JH on December 10, 2019, 09:21:35 AM »
Hi,
I've no experience with multiple os. As I know you must pay attention  with shared memory and also with resets --> the post default procedures resets CPUs on initalisation, so  it can happends that the second OS resets first one on initialisation procedure, if you pay no attention for this.

Please check also:
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor

Maybe it's also good to write on Xilinx forum for this topic.

br
John
9
UltraScale / Re: I am looking for a Pearson who will design the board for FPGA.
« Last post by JH on December 10, 2019, 09:05:29 AM »
Hi,

can you send your specification to:  support@trenz-electronic.de

br
John
10
EDDP-EDPS Support / Re: Updating HW config for SDx
« Last post by Oleksandr Kiyenko on December 10, 2019, 08:03:18 AM »
Hi Henry,

yes, it's possible to implement this function in HLS code, but there are 2 reasons not to do that.
1. Keep all interfaces similar and not much "hardware-specific"
2. If the PWM function will be implemented wrong, (that is more than possible) you will burn the board.

BR
Oleksandr
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