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1

UltraScale / Re: Boot test board for TE0820 module + TE0701 carrier

« Last post by SaW on April 18, 2019, 02:55:58 PM »

Hi,
oh ok thanks.

No on the sd card i only have image.ub like you said on : https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board#TE0820TestBoard-Hardware in the programming part
when i do the flash part, sd is not there and use it after the flash programming is done
best regards
Sarah

2

UltraScale / Re: Boot test board for TE0820 module + TE0701 carrier

« Last post by JH on April 18, 2019, 02:44:51 PM »

Hi,

"
CRITICAL WARNING: [Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.
"
This message comes if the SoC is not initialised and the bootmode is not JTAG --> Xilinx suppress this message only if boot mode is jtag.
So you can normally ignore this message.

Do you have also boot.bin on SD? when your write QSPI flash in SD Boot Mode?

br
John

3

UltraScale / Re: Boot test board for TE0820 module + TE0701 carrier

« Last post by SaW on April 18, 2019, 02:21:55 PM »

Hi John,
I think the problem was the longer path, i tried again today directly from the original folder and it worked too
for the QSPI i just figured that i wasn't enabling the jtag for the module but just using the one of the carrier.. it recognize my device i just have this warning :

CRITICAL WARNING: [Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.
I wonder if this is not an issue because after with the command: TE::pr_program_flash_binfile -swapp u-boot
i get this log :

Code: [Select]

Start Flash Programming with BIN File
Used file:/home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot/Boot.bin
INFO: [TE_PR-41] Start program flash:
  Run "exec program_flash -f BOOT.bin -fsbl /home/petalinux/test_board/prebuilt/software/3eg_1e_2gb/zynqmp_fsbl_flash.elf -flash_type qspi-x8-dual_parallel" in /home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot
  Please Wait..
  ------
INFO: [TE_EXT-5] Command results from program flash "exec program_flash -f BOOT.bin -fsbl /home/petalinux/test_board/prebuilt/software/3eg_1e_2gb/zynqmp_fsbl_flash.elf -flash_type qspi-x8-dual_parallel":
 
****** Xilinx Program Flash
****** Program Flash v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-25163300273AA
Device 0: jsn-JTAG-ONB4-25163300273AA-14710093-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xFF5E0204, data=0x00000555 =====
BOOT_MODE REG = 0x0555
WARNING: [Xicom 50-100] The current boot mode is SD1.
If flash programming fails, configure device for JTAG boot mode and try again.
Downloading FSBL...
Running FSBL...
Finished running FSBL.


U-Boot 2018.01-00073-g63efa8c-dirty (Oct 04 2018 - 08:27:12 -0600)

Model: ZynqMP MINI QSPI
Board: Xilinx ZynqMP
DRAM:  256 KiB
EL Level: EL3
Using default environment

In:    dcc
Out:   dcc
Err:   dcc
ZynqMP> sf probe 0 0 0

SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
ZynqMP> Sector size = 131072.
f probe 0 0 0

Performing Erase Operation...
sf erase 0 2C0000

SF: 2883584 bytes @ 0x0 Erased: OK
ZynqMP> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 7 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 20000

device 0 offset 0x0, size 0x20000
SF: 131072 bytes @ 0x0 Written: OK
ZynqMP> sf write FFFC0000 20000 20000

device 0 offset 0x20000, size 0x20000
SF: 131072 bytes @ 0x20000 Written: OK
ZynqMP> sf write FFFC0000 40000 20000

device 0 offset 0x40000, size 0x20000
SF: 131072 bytes @ 0x40000 Written: OK
ZynqMP> sf write FFFC0000 60000 20000

device 0 offset 0x60000, size 0x20000
SF: 131072 bytes @ 0x60000 Written: OK
ZynqMP> sf write FFFC0000 80000 20000

device 0 offset 0x80000, size 0x20000
SF: 131072 bytes @ 0x80000 Written: OK
ZynqMP> sf write FFFC0000 A0000 20000

device 0 offset 0xa0000, size 0x20000
SF: 131072 bytes @ 0xa0000 Written: OK
ZynqMP> sf write FFFC0000 C0000 20000

device 0 offset 0xc0000, size 0x20000
SF: 131072 bytes @ 0xc0000 Written: OK
ZynqMP> sf write FFFC0000 E0000 20000

device 0 offset 0xe0000, size 0x20000
SF: 131072 bytes @ 0xe0000 Written: OK
ZynqMP> sf write FFFC0000 100000 20000

device 0 offset 0x100000, size 0x20000
SF: 131072 bytes @ 0x100000 Written: OK
ZynqMP> sf write FFFC0000 120000 20000

device 0 offset 0x120000, size 0x20000
SF: 131072 bytes @ 0x120000 Written: OK
ZynqMP> sf write FFFC0000 140000 20000

device 0 offset 0x140000, size 0x20000
SF: 131072 bytes @ 0x140000 Written: OK
ZynqMP> sf write FFFC0000 160000 20000

device 0 offset 0x160000, size 0x20000
SF: 131072 bytes @ 0x160000 Written: OK
ZynqMP> sf write FFFC0000 180000 20000

device 0 offset 0x180000, size 0x20000
SF: 131072 bytes @ 0x180000 Written: OK
ZynqMP> sf write FFFC0000 1A0000 20000

device 0 offset 0x1a0000, size 0x20000
SF: 131072 bytes @ 0x1a0000 Written: OK
ZynqMP> sf write FFFC0000 1C0000 20000

device 0 offset 0x1c0000, size 0x20000
SF: 131072 bytes @ 0x1c0000 Written: OK
ZynqMP> sf write FFFC0000 1E0000 20000

device 0 offset 0x1e0000, size 0x20000
SF: 131072 bytes @ 0x1e0000 Written: OK
ZynqMP> sf write FFFC0000 200000 20000

device 0 offset 0x200000, size 0x20000
SF: 131072 bytes @ 0x200000 Written: OK
ZynqMP> 80%...sf write FFFC0000 220000 20000

device 0 offset 0x220000, size 0x20000
SF: 131072 bytes @ 0x220000 Written: OK
ZynqMP> sf write FFFC0000 240000 20000

device 0 offset 0x240000, size 0x20000
SF: 131072 bytes @ 0x240000 Written: OK
ZynqMP> 90%...sf write FFFC0000 260000 20000

device 0 offset 0x260000, size 0x20000
SF: 131072 bytes @ 0x260000 Written: OK
ZynqMP> sf write FFFC0000 280000 20000

device 0 offset 0x280000, size 0x20000
SF: 131072 bytes @ 0x280000 Written: OK
ZynqMP> 100%
sf write FFFC0000 2A0000 18208

device 0 offset 0x2a0000, size 0x18208
SF: 98824 bytes @ 0x2a0000 Written: OK
ZynqMP> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 37 sec.

Flash Operation Successful
  ------
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
INFO: [Labtools 27-2278] Zynq reset successful
INFO: [TE_PR-1] Reboot Device is done (Note successfully software reboot depends also on devices design).
CRITICAL WARNING: [Labtools 27-3421] xczu3_0 PL Power Status OFF, cannot connect PL TAP.  Check POR_B signal.
INFO: [Labtools 27-1435] Device xczu3 (JTAG device index = 0) is not programmed (DONE status = 0).
INFO: [TE_PR-2] Refresh Device is done.
INFO: [TE_PR-56] Programming elapsed time: 68 seconds
Flash Programming with BIN File finished
/home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot/Boot.bin

But if use the sdcard with image.ub nothing happens.

i tried without opening hardware manager and i get a similar log: (same command)

Code: [Select]

Start Flash Programming with BIN File
Used file:/home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot/Boot.bin
INFO: [TE_PR-41] Start program flash:
  Run "exec program_flash -f BOOT.bin -fsbl /home/petalinux/test_board/prebuilt/software/3eg_1e_2gb/zynqmp_fsbl_flash.elf -flash_type qspi-x8-dual_parallel" in /home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot
  Please Wait..
  ------
INFO: [TE_EXT-5] Command results from program flash "exec program_flash -f BOOT.bin -fsbl /home/petalinux/test_board/prebuilt/software/3eg_1e_2gb/zynqmp_fsbl_flash.elf -flash_type qspi-x8-dual_parallel":
 
****** Xilinx Program Flash
****** Program Flash v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:36:41 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.


Connected to hw_server @ TCP:localhost:3121
Available targets and devices:
Target 0 : jsn-JTAG-ONB4-25163300273AA
Device 0: jsn-JTAG-ONB4-25163300273AA-14710093-0

Retrieving Flash info...

Initialization done, programming the memory
===== mrd->addr=0xFF5E0204, data=0x00000555 =====
BOOT_MODE REG = 0x0555
WARNING: [Xicom 50-100] The current boot mode is SD1.
If flash programming fails, configure device for JTAG boot mode and try again.
Downloading FSBL...
Running FSBL...
Finished running FSBL.


U-Boot 2018.01-00073-g63efa8c-dirty (Oct 04 2018 - 08:27:12 -0600)

Model: ZynqMP MINI QSPI
Board: Xilinx ZynqMP
DRAM:  256 KiB
EL Level: EL3
Using default environment

In:    dcc
Out:   dcc
Err:   dcc
ZynqMP> sf probe 0 0 0

SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
ZynqMP> Sector size = 131072.
f probe 0 0 0

Performing Erase Operation...
sf erase 0 2C0000

SF: 2883584 bytes @ 0x0 Erased: OK
ZynqMP> Erase Operation successful.
INFO: [Xicom 50-44] Elapsed time = 7 sec.
Performing Program Operation...
0%...sf write FFFC0000 0 20000

device 0 offset 0x0, size 0x20000
SF: 131072 bytes @ 0x0 Written: OK
ZynqMP> sf write FFFC0000 20000 20000

device 0 offset 0x20000, size 0x20000
SF: 131072 bytes @ 0x20000 Written: OK
ZynqMP> sf write FFFC0000 40000 20000

device 0 offset 0x40000, size 0x20000
SF: 131072 bytes @ 0x40000 Written: OK
ZynqMP> sf write FFFC0000 60000 20000

device 0 offset 0x60000, size 0x20000
SF: 131072 bytes @ 0x60000 Written: OK
ZynqMP> sf write FFFC0000 80000 20000

device 0 offset 0x80000, size 0x20000
SF: 131072 bytes @ 0x80000 Written: OK
ZynqMP> sf write FFFC0000 A0000 20000

device 0 offset 0xa0000, size 0x20000
SF: 131072 bytes @ 0xa0000 Written: OK
ZynqMP> sf write FFFC0000 C0000 20000

device 0 offset 0xc0000, size 0x20000
SF: 131072 bytes @ 0xc0000 Written: OK
ZynqMP> sf write FFFC0000 E0000 20000

device 0 offset 0xe0000, size 0x20000
SF: 131072 bytes @ 0xe0000 Written: OK
ZynqMP> sf write FFFC0000 100000 20000

device 0 offset 0x100000, size 0x20000
SF: 131072 bytes @ 0x100000 Written: OK
ZynqMP> sf write FFFC0000 120000 20000

device 0 offset 0x120000, size 0x20000
SF: 131072 bytes @ 0x120000 Written: OK
ZynqMP> sf write FFFC0000 140000 20000

device 0 offset 0x140000, size 0x20000
SF: 131072 bytes @ 0x140000 Written: OK
ZynqMP> sf write FFFC0000 160000 20000

device 0 offset 0x160000, size 0x20000
SF: 131072 bytes @ 0x160000 Written: OK
ZynqMP> sf write FFFC0000 180000 20000

device 0 offset 0x180000, size 0x20000
SF: 131072 bytes @ 0x180000 Written: OK
ZynqMP> sf write FFFC0000 1A0000 20000

device 0 offset 0x1a0000, size 0x20000
SF: 131072 bytes @ 0x1a0000 Written: OK
ZynqMP> sf write FFFC0000 1C0000 20000

device 0 offset 0x1c0000, size 0x20000
SF: 131072 bytes @ 0x1c0000 Written: OK
ZynqMP> sf write FFFC0000 1E0000 20000

device 0 offset 0x1e0000, size 0x20000
SF: 131072 bytes @ 0x1e0000 Written: OK
ZynqMP> sf write FFFC0000 200000 20000

device 0 offset 0x200000, size 0x20000
SF: 131072 bytes @ 0x200000 Written: OK
ZynqMP> 80%...sf write FFFC0000 220000 20000

device 0 offset 0x220000, size 0x20000
SF: 131072 bytes @ 0x220000 Written: OK
ZynqMP> sf write FFFC0000 240000 20000

device 0 offset 0x240000, size 0x20000
SF: 131072 bytes @ 0x240000 Written: OK
ZynqMP> 90%...sf write FFFC0000 260000 20000

device 0 offset 0x260000, size 0x20000
SF: 131072 bytes @ 0x260000 Written: OK
ZynqMP> sf write FFFC0000 280000 20000

device 0 offset 0x280000, size 0x20000
SF: 131072 bytes @ 0x280000 Written: OK
ZynqMP> 100%
sf write FFFC0000 2A0000 18208

device 0 offset 0x2a0000, size 0x18208
SF: 98824 bytes @ 0x2a0000 Written: OK
ZynqMP> Program Operation successful.
INFO: [Xicom 50-44] Elapsed time = 37 sec.

Flash Operation Successful
  ------
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/25163300273AA
INFO: [Labtoolstcl 44-664] Will wait up to 180 seconds for booting to complete.
WARNING: [Xicom 50-184] Defaulting to hardware boot mode: SD1.
INFO: [Labtools 27-2278] Zynq reset successful
INFO: [TE_PR-1] Reboot Device is done (Note successfully software reboot depends also on devices design).
INFO: [Labtools 27-1435] Device xczu3 (JTAG device index = 0) is not programmed (DONE status = 0).
create_hw_cfgmem -hw_device [get_hw_devices xczu3_0] -mem_dev [lindex [get_cfgmem_parts {mt25ql256-qspi-x8-dual_parallel}] 0]
INFO: [TE_PR-2] Refresh Device is done.
INFO: [TE_PR-56] Programming elapsed time: 71 seconds
Flash Programming with BIN File finished
/home/petalinux/test_board/prebuilt/boot_images/3eg_1e_2gb/u-boot/Boot.bin

And same result(none) if i use the sdcard with image.ub
for now it is not really a big issue because we would like to use the boot with SD card and it works but in case for later.
Thank you for all the help
best regards
Sarah

4

UltraScale / Re: Boot test board for TE0820 module + TE0701 carrier

« Last post by JH on April 18, 2019, 06:55:43 AM »

Hi,

st i tried also to use the files from the no_prebuild folders and i got an error on the synthesis of the Utility Buffer, the util_ds_buf_0_0_board.xdc wasn't compatible apparently (even if was actually building it for the first time since was the no prebuild project) and it was saying they was an error on the set_property.. but the file was actually empty.

Did you use longer path or space character in your path?
Prebuilt and non prebuilt are the same projects. Only different is the prebuilt folder. I tried out "TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip", it was running.
Can you create the project again (complete new) and send me the logfile (/vlog folder).

What did you see exactly when you open Vivado HW Manager and you try to connect?
br
John

5

UltraScale / Re: Boot test board for TE0820 module + TE0701 carrier

« Last post by SaW on April 17, 2019, 05:20:21 PM »

Hi John,
it worked! i was working with vivado 2018.2 before that's why i used to folder from there but uninstall 2018.2 and add 2018.3 and now it is working

Just i tried also to use the files from the no_prebuild folders and i got an error on the synthesis of the Utility Buffer, the util_ds_buf_0_0_board.xdc wasn't compatible apparently (even if was actually building it for the first time since was the no prebuild project) and it was saying they was an error on the set_property.. but the file was actually empty.
After built the project using the prebuild files and it worked so i just stopped working with the no_prebuild folder.

Only thing is, i tried to boot using the qspi but couldn't... also vivado doesn't recognized my devise.. i wonder if this isn't the problem.

but can at least boot from SDcard, thank you a lot
best regards
Sarah

6

Trenz Electronic FPGA Modules / Re: TE0720: FCLK_CLK1-3 not running

« Last post by narinx on April 17, 2019, 12:39:19 PM »

Worked indeed!
Thanks again!

7

Trenz Electronic FPGA Modules / Re: TE0720: FCLK_CLK1-3 not running

« Last post by narinx on April 17, 2019, 10:15:31 AM »

Hi John,

Thanks!! I did not know this..
Will try to do so and post again when it works :-)

Br,
Hans

8

Trenz Electronic FPGA Modules / Re: TE0720: FCLK_CLK1-3 not running

« Last post by JH on April 17, 2019, 10:06:56 AM »

Hi,

in case you change something which effects PS (PS IP itself, AXI Bus Register Mapping on PL...), you must regenerate FSBL, Uboot...Linux. PS initialisation will be done with FSBL, and also Linux can for example enable/disable the outout CLKs...

So if you start with the reference design, follow the instructions of the wiki documentation (we provide some scripts to automate some steps, but there are also links to do it manually (or check Xilinx  documentation)).

br
John

9

Trenz Electronic FPGA Modules / Re: TE0720: FCLK_CLK1-3 not running

« Last post by narinx on April 17, 2019, 09:50:43 AM »

Thanks for your reply! :-)

No I didn't.  Why is this necessary? Up until now, any change I did on the design (add PLL, change pinout, etc,..) was executed properly by just doing 'cat
fpga_design.bit >> /dev/xdevcfg'.
Is this different for when making changes to the processing system? Sorry I'm still quite new to this :-)
I'm still running the petalinux of the reference design btw.

This wouldn't explain the fact that when changing the clockfrequency, no clocks at all are reported when generating the bitstream.

Br,
Hans

10

Trenz Electronic FPGA Modules / Re: TE0720: FCLK_CLK1-3 not running

« Last post by JH on April 17, 2019, 09:44:07 AM »

Hi,
did you regenerate FSBL, linux(in case you used it) with your new HDF?

br
John