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#21
Trenz Electronic FPGA Modules / My TE0720-04-61C33MAS Starter ...
Last post by DrFluteDos - June 22, 2026, 04:58:09 PMI've successfully booted my TE0720 using an 8G SD card that I last used in a ZedBoard ... just overwriting the boot partition with files from the TE0720 prebuilt reference design.
However, my attempts to use the 64G SDXC card that came with the kit have all failed! According to "Search Assist" the Zynq can't boot from one (see image). Is this correct?
Kind regards
DrFluteDos
However, my attempts to use the 64G SDXC card that came with the kit have all failed! According to "Search Assist" the Zynq can't boot from one (see image). Is this correct?
Kind regards
DrFluteDos
#22
Trenz Electronic FPGA Modules / Re: TE0817-02 — PL logic inter...
Last post by Martin R @Trenz - June 18, 2026, 01:31:24 PMHi Randy,
up to now we are not aware of any hardware issue on TE0817-02 modules.
There are no changes on the board not captured in public available PCN.
To get a more detailed view on the problem, can you please send us the build logs of problematic designs with all warning/error outputs enabled.
Some questions:
Do you utilize the VCU?
Are there any unconstrained path in your design?
Are all timing constraints met?
Can you further send us the Serial numbers (Number on square white QR Sticker) of affected REV02 boards and serial number of your REV01 board used for comparisons.
Please send all together to our support: support@trenz-electronic.de
best regards
Martin
up to now we are not aware of any hardware issue on TE0817-02 modules.
There are no changes on the board not captured in public available PCN.
To get a more detailed view on the problem, can you please send us the build logs of problematic designs with all warning/error outputs enabled.
Some questions:
Do you utilize the VCU?
Are there any unconstrained path in your design?
Are all timing constraints met?
Can you further send us the Serial numbers (Number on square white QR Sticker) of affected REV02 boards and serial number of your REV01 board used for comparisons.
Please send all together to our support: support@trenz-electronic.de
best regards
Martin
#23
UltraScale / TE0802 - Modern setup
Last post by jsolmen - June 17, 2026, 11:39:58 AMHi all,
I am an experienced embedded engineer but I am new with Ultrascale+. The wiki setup seems to be a bit out-of-date, like e.g. using old Ubuntu 22.04.
Are there a more up-to-date starting guide somewhere? Any advice on how to start with this board?
Thanks,
Juan.
I am an experienced embedded engineer but I am new with Ultrascale+. The wiki setup seems to be a bit out-of-date, like e.g. using old Ubuntu 22.04.
Are there a more up-to-date starting guide somewhere? Any advice on how to start with this board?
Thanks,
Juan.
#24
Trenz Electronic FPGA Modules / TE0817-02 — PL logic intermitt...
Last post by randy - June 17, 2026, 07:02:50 AMHello,
We are seeing a hardware-revision-specific issue with the TE0817 SOM and would appreciate guidance from Trenz or other users who may have encountered something similar.
Setup
We have a Vivado/PetaLinux design that has been running reliably on TE0817-01 for a long time. We recently moved to TE0817-02 boards (same carrier, same bitstream/software image where applicable) and started seeing PL-side malfunctions that do not occur on -01.
Symptoms
The specific PL block that fails is not consistent — it changes between Vivado recompiles of the same RTL/IP integration. We have observed, across different builds:
I2C transactions failing, causing sensor module detection to fail at boot.
Debug ILA cores not detecting/triggering correctly; in some builds, one specific ILA clock domain (out of several ILAs running on different clocks) simply does not capture data.
ILA trigger conditions being ignored — the core triggers immediately regardless of the configured trigger condition.
The frmbuf_wr IP issuing AXI write transactions on the bus even though it has not been enabled (no ap_start/enable asserted).
hdmi rx / tx failing
Linux boots normally every time, and PS-side functionality (including PS DDR) is unaffected. Only specific PL logic blocks malfunction, and which block fails appears to vary build-to-build.
This is not limited to a single unit — we have multiple TE0817-02 modules, and the issue is reproducible across all of them. This makes us confident it's a characteristic of the -02 revision itself rather than a single defective board.
Any insight into board-level differences not captured in the public PCN would be very helpful in narrowing this down.
Thank you in advance.
We are seeing a hardware-revision-specific issue with the TE0817 SOM and would appreciate guidance from Trenz or other users who may have encountered something similar.
Setup
We have a Vivado/PetaLinux design that has been running reliably on TE0817-01 for a long time. We recently moved to TE0817-02 boards (same carrier, same bitstream/software image where applicable) and started seeing PL-side malfunctions that do not occur on -01.
Symptoms
The specific PL block that fails is not consistent — it changes between Vivado recompiles of the same RTL/IP integration. We have observed, across different builds:
I2C transactions failing, causing sensor module detection to fail at boot.
Debug ILA cores not detecting/triggering correctly; in some builds, one specific ILA clock domain (out of several ILAs running on different clocks) simply does not capture data.
ILA trigger conditions being ignored — the core triggers immediately regardless of the configured trigger condition.
The frmbuf_wr IP issuing AXI write transactions on the bus even though it has not been enabled (no ap_start/enable asserted).
hdmi rx / tx failing
Linux boots normally every time, and PS-side functionality (including PS DDR) is unaffected. Only specific PL logic blocks malfunction, and which block fails appears to vary build-to-build.
This is not limited to a single unit — we have multiple TE0817-02 modules, and the issue is reproducible across all of them. This makes us confident it's a characteristic of the -02 revision itself rather than a single defective board.
Any insight into board-level differences not captured in the public PCN would be very helpful in narrowing this down.
Thank you in advance.
#25
UltraScale / Re: TE0820 Power Up Issues wit...
Last post by M Kirberg - June 15, 2026, 05:14:18 PMMight be related to TE0820 PCN item from:
https://wiki.trenz-electronic.de/display/PD/PCN-20220725+TE0820-04+to+TE0820-05+Hardware+Revision+Change
#9 Changed reset, enable and power-up structure with resistor R95, added transistor T2, and added resistor R128.
Maybe your control sequence is not compatible anymore?
https://wiki.trenz-electronic.de/display/PD/PCN-20220725+TE0820-04+to+TE0820-05+Hardware+Revision+Change
#9 Changed reset, enable and power-up structure with resistor R95, added transistor T2, and added resistor R128.
Maybe your control sequence is not compatible anymore?
#26
UltraScale / Re: TE0813 app crashes when ac...
Last post by M Kirberg - June 15, 2026, 05:12:01 PMThis is not easy to debug remotely, most likely something very fundamental is missing, have you checked that clocks are running?
#27
UltraScale / Re: TE0813 app crashes when ac...
Last post by bofo - June 12, 2026, 12:04:47 AMI should have mentioned that I am using the cortexr_0 processor. I have also tried the cortexa53_0 processor with similar results.
#28
UltraScale / TE0813 app crashes when access...
Last post by bofo - June 12, 2026, 12:02:46 AMBoards: TE0813 UltraScale+ with TEBF0818 base board
I tried to create a Hello World application using the StarterKit example in Vivado 2023.2, but it did not work. It only reset the board and didn't print anything on the console.
So, I moved on to Vivado/Vitis 2024.1. This worked better and I was able to get Hello World to work. However, I did not use the StarterKit example, I made my own Vivado project.
I then added an extremely simple custom IP block with 8 AXI registers mapped to 0x80000000. When my app tried to access these AXI registers, the program crashes with a DataAbort exception. Here are the steps:
- Build a Vivado project using the same Trenz board for the Project Device as 2023.2 (NOT from the StarterKit)
- TE0813-*-2AE81-A (4GB DDR) with TEBF0818. *SPRT PCB: REV02 (xczu2cg-sfvc784-1-e)
- Added Zynq Processing System and System Reset blocks
- Added an extremely simple custom IP module with 8 AXI R/W registers
- Build a Vitis platform/project using the Vivado .XSA above and the Hello World template
- Run the App
- Console prints "Hello World" and "Successfully ran Hello World application"
- But the system crashes when the application attempts to read one of the AXI registers:
- #define AXI_BASE_ADDR 0x80000000
- Xil_SetMPURegion(AXI_BASE_ADDR, REGION_64K, DEVICE_SHARED);
- Xil_In32(AXI_BASE_ADDR + 0);
- results in a DataAbort exception (fault status = 13)
I added the MPU region which helped me diagnose the fault better, but did not fix the underlying problem.
When the application is run, the "Done" LED on the FPGA board lights briefly, then turns off.
Note that I have built projects this way many times for Zybo and Ultrazed-EV, but this is the first time that I have encountered this. This should have been a pretty quick exercise, but I have been working on this all day with no resolution.
Please let me know if there is anything else I can try.
Thank you.
I tried to create a Hello World application using the StarterKit example in Vivado 2023.2, but it did not work. It only reset the board and didn't print anything on the console.
So, I moved on to Vivado/Vitis 2024.1. This worked better and I was able to get Hello World to work. However, I did not use the StarterKit example, I made my own Vivado project.
I then added an extremely simple custom IP block with 8 AXI registers mapped to 0x80000000. When my app tried to access these AXI registers, the program crashes with a DataAbort exception. Here are the steps:
- Build a Vivado project using the same Trenz board for the Project Device as 2023.2 (NOT from the StarterKit)
- TE0813-*-2AE81-A (4GB DDR) with TEBF0818. *SPRT PCB: REV02 (xczu2cg-sfvc784-1-e)
- Added Zynq Processing System and System Reset blocks
- Added an extremely simple custom IP module with 8 AXI R/W registers
- Build a Vitis platform/project using the Vivado .XSA above and the Hello World template
- Run the App
- Console prints "Hello World" and "Successfully ran Hello World application"
- But the system crashes when the application attempts to read one of the AXI registers:
- #define AXI_BASE_ADDR 0x80000000
- Xil_SetMPURegion(AXI_BASE_ADDR, REGION_64K, DEVICE_SHARED);
- Xil_In32(AXI_BASE_ADDR + 0);
- results in a DataAbort exception (fault status = 13)
I added the MPU region which helped me diagnose the fault better, but did not fix the underlying problem.
When the application is run, the "Done" LED on the FPGA board lights briefly, then turns off.
Note that I have built projects this way many times for Zybo and Ultrazed-EV, but this is the first time that I have encountered this. This should have been a pretty quick exercise, but I have been working on this all day with no resolution.
Please let me know if there is anything else I can try.
Thank you.
#29
Trenz Electronic FPGA Modules / Re: Limited interoperability o...
Last post by Antti Lukats - June 11, 2026, 01:01:44 PM1.3V should be OK
#30
UltraScale / TE0820 Power Up Issues with RE...
Last post by jan.blaesi - June 05, 2026, 04:07:11 PMHi,
we are experiencing some issues with REV04 TE0820 modules.
After a brownout, or occasionally on initial startup, the module sometimes gets stuck, not booting anymore.
The red LED on the long side of the module stays lit up, the boot mode LED blinks as usual.
Doing a longer power cycle (~10 seconds), the module boots up just fine.
Our REV05 modules never show this kind of behaviour, it is just the REV04 ones.
The EN1, RESIN and NOSEQ lines are controlled by a microcontroller, but I did not find any way to get the module out of this state.
Do you have any idea what we could be doing wrong?
Best regards
we are experiencing some issues with REV04 TE0820 modules.
After a brownout, or occasionally on initial startup, the module sometimes gets stuck, not booting anymore.
The red LED on the long side of the module stays lit up, the boot mode LED blinks as usual.
Doing a longer power cycle (~10 seconds), the module boots up just fine.
Our REV05 modules never show this kind of behaviour, it is just the REV04 ones.
The EN1, RESIN and NOSEQ lines are controlled by a microcontroller, but I did not find any way to get the module out of this state.
Do you have any idea what we could be doing wrong?
Best regards