Powering down the PL

[dbarth]

Hey,

I am trying to optimize power consumption on a Zynq application,  by having a Linux/PS part in suspend mode, with no PL running. I would like to reach <50mA while sleeping.

I found a note on the Xilinx forums about cutting power on the PL side, once the system is booted. See https://forums.xilinx.com/t5/Embedded-Linux/Reset-Zynq-FPGA/td-p/315725

Is that doable on a TE0720 module? It seems that all VCCIN lines are shared between PS and PL. Or is there a way to pilot that from the system controller ? Or another 4x5 module better suited to that kind of configuration?

[Thorsten Trenz]

Hi,
this is currently not supported by our modules. If you are interested in custom development service, please sent your specification via email.

Best Regards
Thorsten Trenz