Recent posts

#81

Trenz Electronic FPGA Modules / Re: TEBF0818 CPLD Access not w...

Last post by Antti Lukats - April 15, 2026, 03:48:01 PM

in your screenshot the Lattice programmer did show: FTUSB1 it should however be FTUSB0 !

[TE0726-04]

#82

Trenz Electronic FPGA Modules / Re: Jupyter Demo for ZyncBerry

Last post by Antti Lukats - April 15, 2026, 03:42:08 PM

Sorry, typo. Part is TE0726-04

TE0726-04 is too short for the product code, it only includes the main product code and PCB revision but no infos about assembly option.

So most likely you did choose wrong product code, the most likely right choice is 3 not 4, 4 is for the Z007 version that has different PL size and incompatible bitfiles

[TE0726-04]

#83

Trenz Electronic FPGA Modules / Re: Jupyter Demo for ZyncBerry

Last post by oe8bck - April 15, 2026, 01:09:39 PM

Sorry, typo. Part is TE0726-04

#84

Trenz Electronic FPGA Modules / Jupyter Demo for ZyncBerry

Last post by oe8bck - April 15, 2026, 01:07:52 PM

Hi,

I recently got a ZyncBerry RE0726-04 and wanted to install this demonstration system:
https://www.trenz-electronic.de/Downloads/?path=Trenz_Electronic/Modules_and_Module_Carriers/special/TE0726/Reference_Design/2019.2/zynqberrydemo4

I did not find the correct part number in design_basic_settings.cmd, so I set PARTNUMBER=4. The integration succeeded and then I tried to upload the configuration. But this fails with the message given
ERROR: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device.

Any ideas how to fix this? (I am using Vivado 2019.2)

KR,
Christof

#85

Trenz Electronic FPGA Modules / Re: TE0835-REV02 Power Sequenc...

Last post by mch - March 25, 2026, 11:28:26 AM

Hello Chris,

some of the nets in the schematic of the PCB REV03 have been changed. You can see the following document  for the PCB REV02 at the link below:

https://www.trenz-electronic.de/trenzdownloads/Trenz_Electronic/Modules_and_Module_Carriers/6.5x9/TE0835/REV03/Firmware/Archive/SC-PGM-TE0835-0102_SC835-01_-v.29-01_20_2025.pdf

The "*" symbol indicates that the LED is on, and "o" indicates that the LED is off. I have also written the name of the nets of the PCB REV02 as old names in the current TE0835 CPLD document. Please take a look at the document at the following link:

https://wiki.trenz-electronic.de/display/PD/TE0835+CPLD#TE0835CPLD-ProductSpecification

Best regards,
Mohsen Chamanbaz

#86

Trenz Electronic FPGA Modules / TE0835-REV02 Power Sequencing

Last post by chris_ftl - March 24, 2026, 08:19:26 PM

Hello,

We are trying to bringup a previously not working TE0835-REV02 SOM. This was retired due to a component being knocked off. This was repaired, however the unit will not complete powerup. The status LED blinks twice (IE is on twice). According to this: https://wiki.trenz-electronic.de/display/PD/TE0835+Getting+Started , there is a problem in stage 1, however I am unable to match this documentation to actual nets in the schematic.

Q1: the blink code is fairly inscrutable. Is a * or a "o" the LED on? Does the LED blinking twice actually correspond to stage 1?
Q2: Is there a document that maps these nets to actual schematic nets? Especially the supply enable lines, such as EN_GR1 or EN_PS_PL. These do not match which makes it difficult to find the supply that is amiss.

Thank you,
Chris

#87

Trenz Electronic FPGA Modules / Re: SFP modules I2C design exa...

Last post by RC - March 23, 2026, 11:04:44 AM

Hello,

As we previously mentioned, this design is intended for product testing. So, the I2C operation is actually not necessary for SFP communication. In this design, I2C is used to read/write the EEPROM inside a 10G SFP+ Passive Loopback Testing Module in order to check the contact of the SFP0/1_SCL and SFP0/1_SDA pins.

I have highlighted the relevant IP cores for actual SFP data transmission in the attached image. Please review their connections and settings, and refer to Intel Document 683054 (Intel® Cyclone® 10 GX Transceiver PHY User Guide) for more information.

Regarding NIOS:

In this design, axi_prbs_gtx generates a data sequence. Data is sent to the loopback module via SFP, returned to the transceiver, and sent back to axi_prbs_gtx for comparison. NIOS only controls the start timing of the sequence and reads the comparison results. You can replace the NIOS control with your own pure FPGA logic as preferred

#88

Trenz Electronic FPGA Modules / Re: TEBF0818 CPLD Access not w...

Last post by MA - March 23, 2026, 10:26:55 AM

Hello Fernando,

please ensure that the DIP switch S4.3 is set to "ON"; if it is set to "OFF", this is exactly the behaviour you are experiencing.

• https://wiki.trenz-electronic.de/display/PD/TEBF0818+Getting+Started#TEBF0818GettingStarted-Overview
• Number 7

Best regards,

Manuela

#89

Trenz Electronic FPGA Modules / SFP modules I2C design example

Last post by guirenaud - March 16, 2026, 04:18:00 PM

Hello

We are using the TEIB0006 carrier with the TEI0006 SOM module and start writing HDL code.
In the example design you provided, the implementation of the SFP modules over I2C (over I2C Mux and I2C extender) is done with the Nios core. We'll not use the Nios core in our design.
Is there any other design example you can provide implenting those directly in the FPGA Logic layer ?

Thanks for your help

Guillaume

#90

Trenz Electronic FPGA Modules / TEBF0818 CPLD Access not worki...

Last post by ffloresg - March 11, 2026, 10:20:28 AM

Hello,

I am working with TE0808 on dev board TEBF0818.

I am trying to access and program the Lattice CPLDs on the TEBF0818 development board. I followed steps 1 to 6 in the CPLD Access section of the following guide: https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD+Firmware

However, the Diamond Programmer did not found any device and created a default blank project.

Do you have any idea what might be causing this issue or how it could be resolved?

Thanks in advance.

Best regards,
Fernando