Recent posts

#71

Trenz Electronic FPGA Modules / TE0720 SHA_IO control

Last post by firstname - May 06, 2026, 06:16:56 PM

Hello everyone,my main problem is achieving ability to control onboard ATSHA204A (U10) over SWI via CPLD -> FPGA -> PS
I followed trenz documentation and found an ability to route U10 SDA to XIO4 (PL_pin_M15). In my vivado project I have a System Controller SC0720 + Processing System (Zynq7).
What is the correct way to control U10 under baremetal C driver on PS? Is there any AXI SWI implementations, otherwise how to connect PL_pin_M15 to PS to be able to manage this bidirectional PIN by the right way?
Thanks in advance!

#72

Trenz Electronic FPGA Modules / TE0965 - availability and spec...

Last post by Sascha H - May 06, 2026, 01:03:16 PM

Hi all,
I saw the coming soon tab for Versal 2 board. Any information available about a timeline, pricing and maybe specifications? Looked for a Evaluationboard, but VEK385 from Xilinx is rarely available and expensive. That's the reason I am asking for.

BR
Sascha

#73

Trenz Electronic FPGA Modules / Re: OSPI Flash Initialization ...

Last post by blee - May 06, 2026, 03:01:11 AM

Hi,
I mounted the socket and changed the device to ISSI.
The carrier board name is "AMB0010-01"

I added the Device information at "spi-nor-ids.c" 
        { INFO("is25wx256",  0x9d5b19, 0, 128 * 1024, 256,
                        SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
                        SPI_NOR_HAS_TB | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },
        { INFO("is25wx01g",  0x9d5b1b, 0, 128 * 1024, 1024,
                        SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES |
                        SPI_NOR_HAS_TB | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) },

Thanks

#74

Trenz Electronic FPGA Modules / Re: OSPI Flash Initialization ...

Last post by mch - May 04, 2026, 11:22:10 AM

Hi,

I noticed that you are using an ISSI OSPI memory chip, even though our TE0955 module uses a Micron OSPI memory chip. We have never tested the ISSI OSPI memory chip in our design. Did you solder the OSPI chip onto the module yourself?

Best regards,
Mohsen Chamanbaz

#75

Trenz Electronic FPGA Modules / Re: OSPI Flash Initialization ...

Last post by mch - May 04, 2026, 10:18:16 AM

Hi,

Could you please let me know which carrier board you are using? I tested a new TE0955 module using your tested reference design. It worked perfectly. You can see the results here:

Versal> sf probe 0 0 0
SF: Detected mt35xu02g with page size 256 Bytes, erase size 128 KiB, total 256 MiB

Best regards,
Mohsen Chamanbaz

#76

Trenz Electronic FPGA Modules / OSPI Flash Initialization Fail...

Last post by blee - April 29, 2026, 09:33:01 AM

Hi,
I am experiencing an issue with initializing the OSPI Flash on our Versal-based board
(using the Trenz board TE0955-01 & downloaded file : TE0955-te0955-rd-vivado_2024.2-build_1_20250707150046.zip)

1. Hardware Environment:
   SoC: AMD Versal
   Flash Memory: ISSI 256Mb Octal flash (single die) & ISSI 1Gb Octal Flash (256Mb x 4-die stacked)
   Software: U-Boot / Linux

2. Problem Description:
256Mbit has no issue.
but When executing sf probe in U-Boot with 1Gb Octal Flash, the initialization fails with the following log:
Versal> sf probe 0 0 0
Failed RX dll tuning
DDR tuning failed with error -22
Failed to initialize SPI flash at 0:0 (error 0)

All features of 256M/1G are same except Single Die or Stack Die.
Of course, I added device information correctly into "spi-nor-ids.c or issi.c" also

I am looking forward to your technical guidance on resolving this issue.

Thanks.

#77

Trenz Electronic FPGA Modules / Re: TE0706-04-A Carrier & TE08...

Last post by Antti Lukats - April 17, 2026, 10:28:06 AM

if you want to use the second PHY then you must make sure R19 is installed, R18 is not needed, can be removed, but most likely is OK when it remains
fitted.

#78

Trenz Electronic FPGA Modules / Re: Jupyter Demo for ZyncBerry

Last post by Antti Lukats - April 17, 2026, 10:24:53 AM

Thanks for the quick answer!

Vendor Part Number is TE0726-04-41C98-A (mit Zync 7010-1C)

Obviously the bitfiles are incompatible. I used Vivado 2019.2, the build process up to the integration worked, but bitfile generation failed.

KR, Christof

yes you generated bit file for 007 but you have 010 part, hence the error when booting/configuring

#79

Trenz Electronic FPGA Modules / TE0706-04-A Carrier & TE0820-0...

Last post by Doog - April 16, 2026, 11:09:04 AM

Hi,

I have a TE0706-04-A Carrier board & TE0820-04-3BE21MA SoM.

Are there any board presets / XDC files for this combination.

I am using Viado 2022.2.

Also did I read somewhere that I have to change a resistor on the board.

Thanks in advance for any help.

#80

Trenz Electronic FPGA Modules / Re: Jupyter Demo for ZyncBerry

Last post by oe8bck - April 16, 2026, 12:34:13 AM

Thanks for the quick answer!

Vendor Part Number is TE0726-04-41C98-A (mit Zync 7010-1C)

Obviously the bitfiles are incompatible. I used Vivado 2019.2, the build process up to the integration worked, but bitfile generation failed.

KR, Christof