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#61
Trenz Electronic FPGA Modules / Re: OSPI Flash Initialization ...
Last post by M Kirberg - May 19, 2026, 09:25:02 AMHi,
sorry we cannot really help here.
This can be everything from bad soldering to driver and devicetree settings.
br
sorry we cannot really help here.
This can be everything from bad soldering to driver and devicetree settings.
br
#62
Trenz Electronic FPGA Modules / Re: TE0728 IO_4 & IO_5
Last post by mch - May 18, 2026, 06:03:22 PMHi,
The pins are connected to pins J1-8 and J1-10 of the B2B connector on the TE0728 module. However, these signals are unused on the module and are not connected to any pin or component.
Best regards,
Mohsen Chamanbaz
The pins are connected to pins J1-8 and J1-10 of the B2B connector on the TE0728 module. However, these signals are unused on the module and are not connected to any pin or component.
Best regards,
Mohsen Chamanbaz
#63
Trenz Electronic FPGA Modules / Re: TE0720 SHA_IO control
Last post by mch - May 18, 2026, 05:51:48 PMHi,
1) The ATSHA204A chip package on the TE0720-04 module is SOT. Therefore, the SWI interface is available only in this case. The ATSHA204A is configured by the chip manufacturer. All configuration data can be read; however, some configuration data, such as the serial number and I2C Enable, cannot be written. The I2C Enable byte also cannot be written and can only be read. If bit 0 of the I2C Enable byte is already set to 1, the chip can communicate via the I2C interface; otherwise, the chip will communicate via the SWI interface.
2) That is not a problem. According to the ATSHA204A datasheet, the SDA pin can be pulled up to the same supply voltage or to a lower voltage rail. Please refer to page 25 of the datasheet. The CPLD chip can also operate up to 3.75 V.
Best regards,
Mohsen Chamanbaz
1) The ATSHA204A chip package on the TE0720-04 module is SOT. Therefore, the SWI interface is available only in this case. The ATSHA204A is configured by the chip manufacturer. All configuration data can be read; however, some configuration data, such as the serial number and I2C Enable, cannot be written. The I2C Enable byte also cannot be written and can only be read. If bit 0 of the I2C Enable byte is already set to 1, the chip can communicate via the I2C interface; otherwise, the chip will communicate via the SWI interface.
2) That is not a problem. According to the ATSHA204A datasheet, the SDA pin can be pulled up to the same supply voltage or to a lower voltage rail. Please refer to page 25 of the datasheet. The CPLD chip can also operate up to 3.75 V.
Best regards,
Mohsen Chamanbaz
#64
Trenz Electronic FPGA Modules / Re: TE0965 - availability and ...
Last post by mch - May 18, 2026, 09:39:25 AMHello Sascha,
Could you please contact our sales department? Our sales department email address is:
sales@trenz-electronic.de
Best regards,
Mohsen Chamanbaz
Could you please contact our sales department? Our sales department email address is:
sales@trenz-electronic.de
Best regards,
Mohsen Chamanbaz
#65
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by qwaserdf - May 13, 2026, 08:53:19 PMI see that it also works fine even if I pick the EMIO port.
The only explanation that I see, the CPLD has more connections to the FPGA than the ones shown in the diagram.
Regards.
The only explanation that I see, the CPLD has more connections to the FPGA than the ones shown in the diagram.
Regards.
#66
Trenz Electronic FPGA Modules / Re: TE0720 SHA_IO control
Last post by firstname - May 11, 2026, 06:25:03 PM@mch Thanks a lot, it was useful, now I see 1.8V control on the line. However I have further problem: chip doesn't respond on the line after waking-up process (checked by the oscilloscope).
1) Does ATSHA204A on TE0720-04 configured to SingleWire by default or not? As far as I know, it configures by manufacturer?
2) According to schematics, It must be SingleWire. But there is another question on the surface: Vcc = 3.3V and SDA pulled-up externally to 1.8V as well as CPLD Bank1 for MEM-SHA control.
ATSHA204A default configuration for SWI (when "I2C_Enable<0> = 0") TTL Enable is '1', means "Input level uses the Vcc as reference". Is it good to communicate over SWI pulled-up to 1.8V? Have I missed something?
Looking forward for any useful information and thanks in advance!
1) Does ATSHA204A on TE0720-04 configured to SingleWire by default or not? As far as I know, it configures by manufacturer?
2) According to schematics, It must be SingleWire. But there is another question on the surface: Vcc = 3.3V and SDA pulled-up externally to 1.8V as well as CPLD Bank1 for MEM-SHA control.
ATSHA204A default configuration for SWI (when "I2C_Enable<0> = 0") TTL Enable is '1', means "Input level uses the Vcc as reference". Is it good to communicate over SWI pulled-up to 1.8V? Have I missed something?
Looking forward for any useful information and thanks in advance!
#67
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by qwaserdf - May 11, 2026, 03:30:05 PMI also see here that GPIOs 14 & 15, have the UART_XX labels. What does it mean?
Could it be a mistake, meaning that ID_SCL and ID_SDA, are connected somehow with the CPLD?
#68
Trenz Electronic FPGA Modules / TE0728 IO_4 & IO_5
Last post by remy - May 11, 2026, 01:17:15 PMHi,
What are the IO_4 and IO_5 pins on the TEB0728 carrier board connected/routed to on the TE0728 module?
It's pin J1.8 & J1.10 on the B2B connectors.
Thanks,
Reidar
What are the IO_4 and IO_5 pins on the TEB0728 carrier board connected/routed to on the TE0728 module?
It's pin J1.8 & J1.10 on the B2B connectors.
Thanks,
Reidar
#69
Trenz Electronic FPGA Modules / TE0726 TRM V.3 - MIO48 - MIO49...
Last post by qwaserdf - May 11, 2026, 01:12:17 PMGood morning.
I am struggling to understand, how my project can communicate by USB, through the UART1. If this one exchanges by MIO ports 48 & 49 (verified in design_1_wrapper_io_placed.rpt) and those, ones according to datasheet and electronic schematic, Zynq pins which are connected only to the I2C module:
Pin Pin Memory Bank I/O Type
B12 PS_MIO48_501 501 MIO
D13 PS_MIO49_501 501 MIO
design_1_wrapper_io_placed.rpt
| Pin Number | Signal Name | Pin Name | Use
| B12 | FIXED_IO_mio[28] | PS_MIO48_501 | OUT
| D13 | FIXED_IO_mio[29] | PS_MIO49_501 | IN
datasheet:
Bank 501 MIOs
48 MUX_SCLI2C clock to I2C MUX.
49 MUX_SDAI2C data to/from I2C MUX.
...
Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I 2C multiplexer chip
TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are
routed as follows...
SCH-TE0726-03-07S-1C.pdf
If that I2C (TCA9544APWR) has no connection to the USB/UART (FT2232H-56Q), how do the signals arrive to these MIO ports?
Thanks in advance.
I am struggling to understand, how my project can communicate by USB, through the UART1. If this one exchanges by MIO ports 48 & 49 (verified in design_1_wrapper_io_placed.rpt) and those, ones according to datasheet and electronic schematic, Zynq pins which are connected only to the I2C module:
Pin Pin Memory Bank I/O Type
B12 PS_MIO48_501 501 MIO
D13 PS_MIO49_501 501 MIO
design_1_wrapper_io_placed.rpt
| Pin Number | Signal Name | Pin Name | Use
| B12 | FIXED_IO_mio[28] | PS_MIO48_501 | OUT
| D13 | FIXED_IO_mio[29] | PS_MIO49_501 | IN
datasheet:
Bank 501 MIOs
48 MUX_SCLI2C clock to I2C MUX.
49 MUX_SDAI2C data to/from I2C MUX.
...
Zynq MIO pin 48 (MUX_SCL) and pin 49 (MUX_SDA) are connected to the 4-channel I 2C multiplexer chip
TCA9544A from Texas Instruments having I2C address of 0x70. It has four slave I2C channels which are
routed as follows...
SCH-TE0726-03-07S-1C.pdf
If that I2C (TCA9544APWR) has no connection to the USB/UART (FT2232H-56Q), how do the signals arrive to these MIO ports?
Thanks in advance.
#70
Trenz Electronic FPGA Modules / Re: TE0720 SHA_IO control
Last post by mch - May 07, 2026, 10:56:00 AMHi,
The ATSHA204A in the 3-lead SOT package can only communicate via the Single-Wire Interface and does not support I²C. To use the chip in the Vivado design, the SDA pin of the chip (MEM_SHA), which is connected to CPLD pin N14, must be routed through the CPLD to the FPGA:
MEM_SHA of the crypto chip (SDA) / MEM_SHA (N14) ---------→ CPLD X2 pin (C2) / FPGA M15
To achieve this, the register CR2[3:0] must be set to the value "0010". The following command in the Linux console enables two functions simultaneously:
CPLD pin X2 (C2) as a read path: the FPGA receives the serial data from the crypto chip.
CPLD pin X3 (B1) as a write path: the FPGA can control the crypto chip through the CPLD.
phytool write eth0/0x1A/6 0x0002
0x1A --> Address of the Ethernet PHY chip on the MDIO bus
0x6 --> Address of the CR2 register
(See: https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-SCMDIOInterface)
)
0x0002 --> Corresponds to the bit pattern "0010" for CR2[3:0]
Please note that the X3 pin is referred to as the XIO5 signal in the CPLD documentation.
Since a pull-up resistor is connected to MEM_SHA, the bus operates according to the open-drain principle. After setting CR2[3:0] = "0010", the following applies:
X3 = '0' → The CPLD actively drives MEM_SHA to logic '0' (the FPGA sends a 0 to the crypto chip)
X3 = '1' → The CPLD places MEM_SHA into High-Z state → the pull-up resistor pulls the line to logic '1' (the FPGA sends a 1 to the crypto chip)
Reading the chip response via CPLD pin X2 (C2) and FPGA pin M15 is only possible when X3 = '1' (High-Z), because only in this state can the crypto chip control the line itself. As long as X3 = '0', the CPLD actively drives SHA_IO to '0', and the read path will also always return '0', regardless of the chip state.
The X3 pin (B1) of the CPLD chip is directly connected in the hardware design to FPGA pin N15.
Communication with the ATSHA204A therefore takes place through two FPGA pins:
FPGA pin (N15) / CPLD pin X3 (B1) ====> FPGA transmits to the chip (write)
FPGA pin (M15) / CPLD pin X2 (C2) ====> FPGA reads the MEM_SHA line state (reading is only meaningful when X3 = '1')
You can control the crypto chip either with a bare-metal C driver or under Linux using a single-wire interface IP core in the Vivado design. However, we do not have any example code or reference project available for the single-wire communication interface.
Best regards,
Mohsen Chamanbaz
The ATSHA204A in the 3-lead SOT package can only communicate via the Single-Wire Interface and does not support I²C. To use the chip in the Vivado design, the SDA pin of the chip (MEM_SHA), which is connected to CPLD pin N14, must be routed through the CPLD to the FPGA:
MEM_SHA of the crypto chip (SDA) / MEM_SHA (N14) ---------→ CPLD X2 pin (C2) / FPGA M15
To achieve this, the register CR2[3:0] must be set to the value "0010". The following command in the Linux console enables two functions simultaneously:
CPLD pin X2 (C2) as a read path: the FPGA receives the serial data from the crypto chip.
CPLD pin X3 (B1) as a write path: the FPGA can control the crypto chip through the CPLD.
phytool write eth0/0x1A/6 0x0002
0x1A --> Address of the Ethernet PHY chip on the MDIO bus
0x6 --> Address of the CR2 register
(See: https://wiki.trenz-electronic.de/display/PD/TE0720+CPLD#TE0720CPLD-SCMDIOInterface)
)
0x0002 --> Corresponds to the bit pattern "0010" for CR2[3:0]
Please note that the X3 pin is referred to as the XIO5 signal in the CPLD documentation.
Since a pull-up resistor is connected to MEM_SHA, the bus operates according to the open-drain principle. After setting CR2[3:0] = "0010", the following applies:
X3 = '0' → The CPLD actively drives MEM_SHA to logic '0' (the FPGA sends a 0 to the crypto chip)
X3 = '1' → The CPLD places MEM_SHA into High-Z state → the pull-up resistor pulls the line to logic '1' (the FPGA sends a 1 to the crypto chip)
Reading the chip response via CPLD pin X2 (C2) and FPGA pin M15 is only possible when X3 = '1' (High-Z), because only in this state can the crypto chip control the line itself. As long as X3 = '0', the CPLD actively drives SHA_IO to '0', and the read path will also always return '0', regardless of the chip state.
The X3 pin (B1) of the CPLD chip is directly connected in the hardware design to FPGA pin N15.
Communication with the ATSHA204A therefore takes place through two FPGA pins:
FPGA pin (N15) / CPLD pin X3 (B1) ====> FPGA transmits to the chip (write)
FPGA pin (M15) / CPLD pin X2 (C2) ====> FPGA reads the MEM_SHA line state (reading is only meaningful when X3 = '1')
You can control the crypto chip either with a bare-metal C driver or under Linux using a single-wire interface IP core in the Vivado design. However, we do not have any example code or reference project available for the single-wire communication interface.
Best regards,
Mohsen Chamanbaz