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#51
Trenz Electronic FPGA Modules / Re: Limited interoperability o...
Last post by Antti Lukats - May 27, 2026, 08:16:20 AMyes the operation is only possible for MIPI and HDMI boards. The 1.3V is not so good but Agilex has no other options
#52
Trenz Electronic FPGA Modules / Re: TE0701 Rev7 Release Date
Last post by mch - May 26, 2026, 10:32:16 AMHello Tobias,
Could you please contact our sales department? Our sales department email address is:
sales@trenz-electronic.de
Best regards,
Mohsen Chamanbaz
Could you please contact our sales department? Our sales department email address is:
sales@trenz-electronic.de
Best regards,
Mohsen Chamanbaz
#53
Trenz Electronic FPGA Modules / Limited interoperability of CR...
Last post by FvM - May 23, 2026, 12:03:56 PMHello,
I recently ordered CR00200-01 (1 Gbps Ethernet) and CR00049-01 eMMC CRUVI modules, considering to use them for test setups with AXE5000 Agilex 5 Eval Board.
Looking into possible implementation details, I notice now that these modules can be most likely not used with Agilex FPGA Boards due to incompatible Vadj range. Agilex 3 and 5 have a maximal VCC_HSSI of 1.3 V while Marvell 88E1512 PHY on CR00200 and eMMC on CR00049 require at least 1.8 V IO supply.
I might be that operation at unspecified lower VDDO respectively VCCQ is possible, I didn't yet test.
What I would expect however is a hint in module product information about minimal required Vadj.
Any experience with operation of CRUVI modules beyond 1.8 V Vadj?
Regards
Frank
I recently ordered CR00200-01 (1 Gbps Ethernet) and CR00049-01 eMMC CRUVI modules, considering to use them for test setups with AXE5000 Agilex 5 Eval Board.
Looking into possible implementation details, I notice now that these modules can be most likely not used with Agilex FPGA Boards due to incompatible Vadj range. Agilex 3 and 5 have a maximal VCC_HSSI of 1.3 V while Marvell 88E1512 PHY on CR00200 and eMMC on CR00049 require at least 1.8 V IO supply.
I might be that operation at unspecified lower VDDO respectively VCCQ is possible, I didn't yet test.
What I would expect however is a hint in module product information about minimal required Vadj.
Any experience with operation of CRUVI modules beyond 1.8 V Vadj?
Regards
Frank
#54
Trenz Electronic FPGA Modules / TE0701 Rev7 Release Date
Last post by TobiasWinkler - May 22, 2026, 04:01:46 PMI'd like to purchase the TE0701 with a HPC FMC connector.
Is there already a release date for the seventh revision?
Best regards
Tobias
Is there already a release date for the seventh revision?
Best regards
Tobias
#55
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by MA - May 22, 2026, 07:09:33 AMHi,
The TE0726-03R is an assembly variant without Ethernet, USB and HDMI. The schematics and assembly documentation for your specific assembly variant can be found under the following link.
However, based on the DDR size, I assume that you may not be able to use the HDMI interface in the same way as on the standard variant (128 MB instead of 512 MB DDR).
Best regards
The TE0726-03R is an assembly variant without Ethernet, USB and HDMI. The schematics and assembly documentation for your specific assembly variant can be found under the following link.
However, based on the DDR size, I assume that you may not be able to use the HDMI interface in the same way as on the standard variant (128 MB instead of 512 MB DDR).
Best regards
#56
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by qwaserdf - May 21, 2026, 06:03:15 PMHello,
It was only out of curiosity, since I realized that regardless of which MIO port I select for the UART1 communication, or even if I use the EMIO one, this is configured correctly. That feels a bit strange to me.
Besides that, there is something else I would like to ask about this board, if you don't mind. Please let me know if I should open a new topic for this question.
The version I bought of the ZynqBerry only has the J1 connector, and it also lacks many of the other resistors (purchased years ago from DigiKey: https://www.digikey.at/en/products/detail/trenz-electronic-gmbh/TE0726-03R/6141394).
I would like to know whether mounting the HDMI connector and the adjacent EMI filters would be enough to enable HDMI functionality, or if any other indispensable components are also missing.
Best regards.
It was only out of curiosity, since I realized that regardless of which MIO port I select for the UART1 communication, or even if I use the EMIO one, this is configured correctly. That feels a bit strange to me.
Besides that, there is something else I would like to ask about this board, if you don't mind. Please let me know if I should open a new topic for this question.
The version I bought of the ZynqBerry only has the J1 connector, and it also lacks many of the other resistors (purchased years ago from DigiKey: https://www.digikey.at/en/products/detail/trenz-electronic-gmbh/TE0726-03R/6141394).
I would like to know whether mounting the HDMI connector and the adjacent EMI filters would be enough to enable HDMI functionality, or if any other indispensable components are also missing.
Best regards.
#57
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by MA - May 21, 2026, 10:54:12 AMHi,
At the moment, I am not fully sure if I understand the goal of the exercise correctly.
So your intention is to disconnect UART1 from J1 and verify that no UART outputs (e.g. the "H" character) appear anymore on the console at your PC?
If you are still receiving UART output on the console despite UART1 being disabled on MIO8 and MIO9, this could also be related to the signal levels of the UART connection routed through the CPLD.
Regards,
Manuela
At the moment, I am not fully sure if I understand the goal of the exercise correctly.
So your intention is to disconnect UART1 from J1 and verify that no UART outputs (e.g. the "H" character) appear anymore on the console at your PC?
If you are still receiving UART output on the console despite UART1 being disabled on MIO8 and MIO9, this could also be related to the signal levels of the UART connection routed through the CPLD.
Regards,
Manuela
#58
Trenz Electronic FPGA Modules / Re: PYNQ on TE0726-03
Last post by oe8bck - May 19, 2026, 03:07:54 PMHi,
I would like to test PYNQ on a TE0726-04, did anybody have succeeded on this?
BT,
Christof
I would like to test PYNQ on a TE0726-04, did anybody have succeeded on this?
BT,
Christof
#59
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by qwaserdf - May 19, 2026, 01:16:41 PMThank you Manuela for your answer.
Please have a look on this image:
What you see there is the output of a design that sends the UART1 connection through the EMIO, in the PL the signal is modified (making it '1' an immediate cycle after it is driven to '0') and connected to two GPIOs.
Despite the signal is corrupt and I am not connecting anything to those GPIOs, I keep receiving the "H" character in the upside terminal. So there must be a path somewhere else.
You are saying that the connection is made through the MIO8 and MIO9. However theoretically if I don´t enable it, they're not connected (ps7_init.html):
So it is confirmed despite of the selected port for the UART1, the connection through the MIO8-9 is established? Keeping the UART1 through the EMIO, and selecting MIO8-9 for CAN peripheral (as I see it's their other only purpose), will provoke that I don´t receive the messages anymore?
Regards.
Please have a look on this image:
What you see there is the output of a design that sends the UART1 connection through the EMIO, in the PL the signal is modified (making it '1' an immediate cycle after it is driven to '0') and connected to two GPIOs.
Despite the signal is corrupt and I am not connecting anything to those GPIOs, I keep receiving the "H" character in the upside terminal. So there must be a path somewhere else.
You are saying that the connection is made through the MIO8 and MIO9. However theoretically if I don´t enable it, they're not connected (ps7_init.html):
So it is confirmed despite of the selected port for the UART1, the connection through the MIO8-9 is established? Keeping the UART1 through the EMIO, and selecting MIO8-9 for CAN peripheral (as I see it's their other only purpose), will provoke that I don´t receive the messages anymore?
Regards.
#60
Trenz Electronic FPGA Modules / Re: TE0726 TRM V.3 - MIO48 - M...
Last post by MA - May 19, 2026, 10:18:45 AMHi,
I am not entirely sure if I understood your question correctly.
The USB connector (J1) is connected to the FTDI device and provides:
one interface via JTAG to the Zynq (TCK, TDI, TDO and TMS)
as well as one UART interface via the signals C_TCK and C_TDI, which are routed through the CPLD and connected to MIO8 and MIO9 in the PS, where they are configured as UART1.
MIO48 and MIO49 are connected to I2C1
Best regards,
Manuela
I am not entirely sure if I understood your question correctly.
The USB connector (J1) is connected to the FTDI device and provides:
one interface via JTAG to the Zynq (TCK, TDI, TDO and TMS)
as well as one UART interface via the signals C_TCK and C_TDI, which are routed through the CPLD and connected to MIO8 and MIO9 in the PS, where they are configured as UART1.
MIO48 and MIO49 are connected to I2C1
- https://wiki.trenz-electronic.de/display/PD/TE0726+CPLD#TE0726CPLD-UART
- https://wiki.trenz-electronic.de/display/PD/TE0726+Zynqberry+Demo1
Best regards,
Manuela