Author Topic: SDRAM Interface  (Read 111 times)

asc1

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SDRAM Interface
« on: June 15, 2018, 04:12:17 PM »
CYC1000 comes with an SDRAM chip, but there is no SDRAM core in the Quartus IP library. According to the NIOS ref design it should be possible to use a NIOS based controller, however the ref design is incomplete (to my taste) and checking the pinout revelas that there is no clock for the SDRAM chip coming from the FPGA.
Please clarifiy how to properly use the SDRAM, preferable also without NIOS.
I use the CYC1000 for teaching and have some designs running on it, so the rest of the board is nice (few more switches would be good, though)