Author Topic: SDRAM Interface  (Read 719 times)

asc1

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SDRAM Interface
« on: June 15, 2018, 04:12:17 PM »
CYC1000 comes with an SDRAM chip, but there is no SDRAM core in the Quartus IP library. According to the NIOS ref design it should be possible to use a NIOS based controller, however the ref design is incomplete (to my taste) and checking the pinout revelas that there is no clock for the SDRAM chip coming from the FPGA.
Please clarifiy how to properly use the SDRAM, preferable also without NIOS.
I use the CYC1000 for teaching and have some designs running on it, so the rest of the board is nice (few more switches would be good, though)

Minatsu

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Re: SDRAM Interface
« Reply #1 on: September 07, 2018, 08:24:04 AM »
I got my CYC1000 last week, and found the same issue.

I fixed the reference NIOS design to work with on-board SDRAM:
https://github.com/MinatsuT/CYC1000_SDRAM

Primary changes from the original design are as follows:
  • SDRAM related port directions (input or output) defined in the top module (top.v) are fixed.
  • A phase shifted PLL output and its output pin are added to provide a clock for SDRAM.
  • Sample Eclipse projects are included, which use SDRAM as a main memory.

Enjoy it ;)

microchaos

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Re: SDRAM Interface
« Reply #2 on: September 13, 2018, 08:48:28 PM »
Hi Minatsu,

  Thank you for sharing your design!
  Just cloned your design from github. Quick check shows that MEM_CLK pin is not assigned to the physical pin. This is excerpt from qsf file:
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to MEM_CLK

  When checking pin planer pin B14 is shown as unsigned as well.

Minatsu

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Re: SDRAM Interface
« Reply #3 on: September 19, 2018, 03:24:46 PM »
Hi microchaos,

Thank you for checking my design.

I am new at FPGA, and interested in fitter's automatic assignment ability because I found that PIN_B14 has "PLL2_CLKOUTp" function.
It seems that PLL2 is intended to be used as a clock generator for SDRAM on CYC1000.

I assigned a location of my_pll (pll0) to PLL2 by assignment editor, and leaved MEM_CLK unassigned.
Then I found that MEM_CLK is automatically assigned to PIN_B14 by fitter at compilation time.

However, of course it is better to assign MEM_CLK to PIN_B14 explicitly to avoid any unexpected behavior, so I updated my design on github.