Why this slice was not connected ?

[jinyu]

Hi,
      I noticed  there is a port was not connected.Does it affect the vivado project?

      project location( ../IIoT-EDDP/HLS/ARTY_Z7_FULL/vivado)

      AXI Register Bank 16/16 IP core ,which PIN WR14 connect to a slice ,but the slice connected nothing.
     
      can you give me some advice?

regards

[JH]

Hi,
i think it's not longer used. Unused logic will be removed during synthesis.
br
John

[jinyu]

hi，

I understand , you solved my problem. thank you very much.