Author Topic: Trying to get simplest possible example to work on te0726-03m  (Read 6550 times)

ElkMaster3000

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Trying to get simplest possible example to work on te0726-03m
« on: January 18, 2018, 07:43:02 PM »
Hello, I'm trying to get the simplest possible Verilog program to run on my te0726-03m. More specifically, I'm trying to follow https://www.beyond-circuits.com/wordpress/tutorial/tutorial1/. The problem I have is about pin assignments and io-standards.

I noticed that other boards have useful pre-built XDC files, such as e.g. https://github.com/Digilent/digilent-xdc. Does the te0726-03m have something similar, or does one have to go through some (hidden) data sheet somewhere to figure out which io-standard to assign various pins?

I also noticed this wiki page: https://wiki.trenz-electronic.de/display/PD/LED+Blinky+Tutorial. There it is said that:

Quote
In Zynq System the main System Clock is connected PS (Processing Subsystem) and is not directly available to the PL (Programmable Logic - FPGA) unless the PS has enabled it during FSBL boot process. So if we have a generic Zynq Board then we can not expect to have clocks available to the FPGA until the Processing system has provided them. There may be clocks available to the PL that are active when the PS is not booted but this not a requirement.

If our goal is to make a LED to blink (from PL in Zynq Device), then the safest way is to use FPGA Configuration Master Clock this clock is always available and accessible in the same way, we do not need to know any specifics to the board we have and we do not depend on PS init done by FSBL.

This might be a problem here, because I have not configured the PS in any way (because I was hoping one wouldn't have to just to get the simplest possible program to run). Is there some clock one can use on the te0726-03m without configuring/starting/interacting/understanding the PS?

Lastly, I don't have any LEDs ... I was hoping that the Vivado IDE would be able to do something similar to what is done in the end of this video (when the board is plugged in over USB to my computer, without external extra JTAG components): https://www.youtube.com/watch?v=TlWlLeC5BUs. But I haven't been able to get that far because Vivado do not want to generate a bitstream because of missing pin assignments.

So concretely I just need to understand what clock to use, and find some pins that can be used in some Vivado GUI similar to what is seen in the linked YouTube video (include which io-standard to use everywhere). Does anyone have any pointers? Thanks.

JH

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #1 on: January 19, 2018, 09:46:23 AM »
Hello,

we have some reference design to start (include board part files for correct PS settings on vivado):
2017.4 reference design is in preparing with wiki documentation instead of instruction on the download page.

You should use Vivado Block Design (in the most cases easier). You can create own Block Design IPs, which can be written in verilog.
You find some xilinx reference on:
Search for UG number and select your Vivado Version on the URL of the document or use Xilinx DocNav.


On Zynq, PS must be initialized to get PS CLKs running. Normally this is done by FSBL. Configure Bitfiles does not initialise PS part.



For XDC: We provide a master pinout Excel Viewer (only Loc constrain)/Generator :We have also Schematics available:
br
John



ElkMaster3000

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #2 on: January 19, 2018, 10:16:00 AM »
Thank you for your help. Am I understanding you correctly if I interpret you as saying that this board, with the Zynq chip, is not usable as "plain" FPGA without an ARM core. I.e., I must initialize and configure the ARM core to be able to use the FPGA part of the chip (because there's no clock available otherwise)? For example, here I would like to just build the LED example, not build an AXI4 peripheral (to the ARM core I assume) as the wiki links tells me to do.

JH

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #3 on: January 19, 2018, 10:30:10 AM »
Hi,
on normal design flow yes. For example Zynq PS is need to load programming file from flash. There are much ways to start design.

You can do following (easy way but maybe not complete correct way):
  • Create Design with our Board Part (for exampe 2017.1 design or wait for 2017.4)
  • Remove all IPs (only Zynq must be there)
  • Disable PS-PL AXI (On Zynq PS setup)
  • Enable all 4 PS-PL CLKs and set your preferred CLK frequency
  • Generate Design
  • export hdf to SDK
  • generate fsbl and boot.bin
  • configure flash
  • --> on power on PS is initialised by Flash design and you can overwrite PL part with bitfile programming, which used this clks
br
John
« Last Edit: January 19, 2018, 10:58:14 AM by JH »

ElkMaster3000

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #4 on: January 19, 2018, 12:52:43 PM »
I see, thank you. I will do these simple examples on a simpler board (without a PS) then and possibly come back to this board later! :)

JH

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #5 on: January 19, 2018, 01:02:38 PM »
Yes,
if PS is not needed pure FPGA board is a better choice.

If you start with ZynqBerry,  use our reference design at first. I will try to create a first 2017.4 design with wiki description a little earlier.

br
John

offroad

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #6 on: May 01, 2018, 04:00:20 PM »
Hi,

I'm trying the same thing on the TE0726. Upload to volatile memory via SDK "program FPGA" works as expected, both for PL and PS if I use e.g. the Hello-World template.
Now I need to write it to Flash, and the list from the earlier post  makes sense - this is exactly what I want.
So I create a FSBL project from the template, and in SDK:"Create boot image" I add it as "bootloader", then the .bit file as datafile (is this correct)?

The main problem is that I cannot write to flash memory at all:
Both from Vivado's HW manager (attach memory component, right-click the s25fl128s-... part ,"program configuration memory device") and from SDK ("program Flash"), the progress bar in the popup window never moves past the first few pixels. When I abort, I get these messages

WARNING: [Xicom 50-100] The current boot mode is QSPI.
If flash programming fails, configure device for JTAG boot mode and try again.
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
ERROR: [Labtools 27-3419] Disconnecting from hw_server since it's not responding to requests.  It is recommended to investigate hw_server to find any issues.
ERROR: [Xicom 50-162] Timed out while waiting for uboot prompt.
Problem in running uboot
Flash programming initialization failed.

ERROR: [Labtools 27-3161] Flash Programming Unsuccessful


I understand the first suggestion "JTAG boot mode" is not an option.
Now what about the "uboot" messages? Is u-boot required for a PL-only design (except FSBL)?

I'm using Vivado 2018.1. The project was created from scratch using the PS "preset" for TE0726. Everything else I've tried works OK so far, only writing to flash fails.
Any hints would be appreciated.

offroad

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #7 on: May 01, 2018, 09:10:50 PM »
So I did some more experiments with pre-built binaries and noticed that the Xilinx Flash programmer seems to use U-boot commands (which then fail with JEDEC ID = 00 00 00 - apparently the flash chip isn't recognized - but that's a different problem, possibly mismatch between U-boot or FSBL and the board hardware?).
What would be the correct way to upload a non-Linux-based design? First boot into Linux, then flash from there? ("Boot into Linux" is another unsolved problem for me since a Windows 10 update broke the Vivado installations before 2017.4 but again, that's another problem).

offroad

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #8 on: May 01, 2018, 10:55:23 PM »
A quick follow-up: I soldered wires to the hardware JTAG port to a TE0790 adapter with J15 closed (pulled to 3.3 V)
>> JTAGENB, when low, TDO, TDI, TMS and TCK function as GPIOs, J15

Now I get a similar JEDEC ID 00 00 00 error as the earlier uboot experiment, which is most likely caused by incorrect flash configuration of my PS.
Comments are still appreciated - I'm sure there must be a way to program Zynq flash without external JTAG or Linux.

JH

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #9 on: May 02, 2018, 08:19:16 AM »
Hi,

did you take the important note for special FSBL from 2017.4 reference design into account (at the end of this chapter):

Xilinx has change Flash programming since 2017.3.
There are 2 problems with newer Vivado we have solved with our special FSBL for Flash programming:
  • It's not necessary to change boot mode to JTAG (--> changed on FSBL Code)
  • Generate this special Flash FSBL with Flash Feedback CLK enabled on PS, to get new Xilinx Micro Uboot running.

For baremetal app you can also use this app. Use normal FSBL, Bitfile and your App in the boot.bin and use the special FSBL for Flash on Vivado or SDK GUI.
I did not test with 2018.1, but I think this should also work. We will skip 2018.1 and will test 2018.2 as next supported version.


br
John





offroad

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Re: Trying to get simplest possible example to work on te0726-03m
« Reply #10 on: May 02, 2018, 07:12:04 PM »
Hi John,

thank you very much.
Using the prebuilt zynqmp_fsbl_flash solved the problem. Now flashing (+verify) completes on 2018.1, both with jumpered JTAG and through USB.