TE0722 DIPFORTy1 with Xmod-FT2232H

[netnazgul]

Hello.
We've bought a set of TE0722 modules to use for some of our projects. To work with it we also got TE0790's (Xmod; to not bother ourselves with rerouting native Xilinx platform cable modules (and they are also used for other applications).
As I understand it correctly, Xmod doesn't work with TE0722 out of the box because of latter's custom JTAG pinout. Page here says it's done via freeware Lattice Diamond Programmer tool. However there is currently some kind of problem with their website as I can't download anything there for 3 days already (every product download just returns "Page Not Available") and their support is rather slow on action.

Is it possible to obtain Lattice Diamond Programmer from your site or any other mirror? This issue hinders further development because I can't access the board without Xmod (looks like I'd have to reroute either Xilinx or Xmod with patchcords after all).

[JH]

Hello,

did you used this link:
http://www.latticesemi.com/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx

Scroll down and press on the name "Programmer Standalone 3.9 64-bit for Windows " in the table.
The window will changing to license Agreement.

The download works on my place. Or can you use a other browser?

br
John

[netnazgul]

Yes, that was exactly what I was trying to do (I also used the page http://www.latticesemi.com/programmer). It redirects me here: http://www.latticesemi.com/PageNotAvailable.aspx.

[JH]

This works also.
I used: http://www.latticesemi.com/programmer
Scrolled down to the table at the end
Pressed on "Programmer Standalone 3.9 64-bit for Windows "
    --> Link Address: http://www.latticesemi.com/view_document?document_id=52058
Goes to license agreement page: http://www.latticesemi.com/FileExplorer.aspx?media={D1E1C570-75F1-4D46-B8EF-1FB222AE040C}&document_id=52058

Can you try this . Or change browser.
br
John

[netnazgul]

Tried it from Firefox, Chrome and IE - with the same result across browsers. Also tried to create another account stating residence as California (I'm from Belarus, which sometimes is given restricted access to certain tools due to politic issues), same result.

All in all I suspect it's something with the website and/or newly created accounts. I saw a post on some IC dev forum from a week ago stating that it's impossible to download from Lattice.

[JH]

Hi,

sorry, if there are some restrictions for download, we can't help. You must try to get access from lattice support for this.

br
John

[netnazgul]

OK, I got past that point, reprogrammed the Xmod and connected to Zynq in Vivado.

Now there are some stability problems:

• Vivado periodically reconnects to digilent saying
  

  ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/251633002377A
• Zynq XADC monitor reports temps up to 70C
• After 5 minutes or so Zynq can bug out and report "not programmed" until I reconnect it with supply

I'm running shipped design and supplying TE0722 through Xmod USB and 1.8M USB cable from PC. Is it just a power issue?

[JH]

Hi,
which assembly variant did you use?

How did you connect TE0790 to TE0722, did you use separate power supply or did you use XMOD (this delivers max 100mA)?
What's the XMOD DIP setting?

More information to TE0722: https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=36243771

br
John

[netnazgul]

I have TE0722-02I variant (dual-core industrial grade).
It's powered through XMOD (switches 1, 3 and 4 are ON on XMOD). I've seen a notification "Supply through xmod is not recommended" so I suppose it's the reason.
I also switched 1.8M USB cable to 1.0M one and now power is more stable, no reconnects and shipped design doesn't bug out. Will get external supply so that no problems with power arise, at least I've got it working.

Connected TE0722 to PC UART, although I don't get "TE0722 FSBL for DDR less Zynq ..." message, but "Secondary FPGA Image Loaded..". Probably I'm not rebooting it correctly (or it's not in the shipped design but rather a separate design primer that should be loaded explicitly)

A quick question on DDR-less architecture - how much memory is available for user SW application in this design?

[JH]

Which USB Hub did you use on your PC? 1.0, 2.0 or 3.0?

"Secondary FPGA Image Loaded.." is delivered design. This can get access to SD. We planning to generate a reference design with this function, but i can tel you a timeline for this.

Memory: OCM (256kB, but you can not use all) or instantiate Block RAM on PL part. You has also QSPI and SD available for storage.

Basic Zynq Documentation: https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

You can also try to implement this:
http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Booting+and+Running+Without+External+Memory+Tech+Tip

br
John

[netnazgul]

Is there an easier example of running custom application from OCM without it being copied to DDR?
The latter link requires a lot of changes to reference code which are not detailed apart from the sources, and source archive is not available without registration and clearance on xilinx website.

[JH]

Hi,

write your app content  into FSBL Source code.
See FSBL template of the Trenz Reference Design.

br
John

[netnazgul]

I've enabled FSBL_DEBUG and FSBL_DEBUG_INFO, this is the output I get from running my version of modified FSBL (as per this link https://www.xilinx.com/support/answers/56044.html):

Code: [Select]

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00002002
Data Word Len: 0x00002002
Partition Word Len:0x00002002
Load Addr: 0xFFFF0000
Exec Addr: 0xFFFF0000
Partition Start: 0x000333F0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFFE6998
Application
INVALID_LOAD_ADDRESS_FAIL
FSBL Status = 0xA00F
PCAP:StatusReg = 0x40000F30
PCAP:device ready
PCAP:Clear done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07I assume I don't even reach FsblHookBeforeHandoff function where user program is supposed to be written according to Trenz Reference Design.

If I'm wrong, where can I place a call/loop to user program code?

[netnazgul]

btw, do I even need fsbl to run everything correctly? Or I can just have an application call ps7_init() (in "Hello World" it is commented out) and then write user code afterwards? Because I don't see a lot of use for FSBL in everything is just run from OCM and other FSBL functions are not really used.

Main reason for it is that I cannot run/debug FSBL template from SDK, it says there is no suitable executable for that.

[netnazgul]

Ok, I was not correct, FSBL can be run/debugged from SDK.

Here is the log from running FSBL in SDK (most of it is not shown when run from flash, I assume that UART doesn't catch up prior to the latter stages of FSBL?), no application attached:

Code: [Select]

Xilinx First Stage Boot Loader
Release 2017.1  Oct 10 2017-10:16:26
TE0722 FSBL Modification: DDR Init Check is disabled and define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0 is added.
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x1 0x20 0x18
SPANSION 128M Bits
QSPI is in single flash connection
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60500000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 2
Partition Number: 1
Header Dump
Image Word Len: 0x0002CE18
Data Word Len: 0x0002CE18
Partition Word Len:0x0002CE18
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFF72D76
Bitstream
In FsblHookBeforeBitstreamDload function
юCAP:StatusReg = 0x40000F30
DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Handoff Address: 0x00000000
In FsblHookBeforeHandoff function
---------------------------------
TE0722 FSBL for DDR less Zynq ...
---------------------------------
No Execution Address JTAG handoff
Looks like everything runs as it is supposed to.
The question still stands - where's the best place for user code in FSBL? Should I insert a jump to user program into FsblHandoffJtagExit loop?

[JH]

There are many ways, see Zynq TRM and Xilinx User Guides.
FSBL is the easiest way to do this. If you boot from Flash instead of SDK, FSBL is used to initialize PS, load bitfiles and start apps (normally it's put app into DDR, this is not available on TE0722). You can change this all, but if your app is small, but code into FSBL code is faster.

br
John

[netnazgul]

ok, thank you for the tips, I'll continue to explore the possibilities of the board.
Added usercode jump to one of FSBL hooks, flashed firmware looks to be working ok (just a test piece of code writing uptime through UART via internal cpu timer).

[netnazgul]

Didn't think it will be that quick, but here are two another quirks with TE0722:
1. I've removed Xmod and applied an external supply to 3.3V pin (from Keithley source), but TE0722 does not boot up - red LED light is lit. However it boots up ok when on external supply, Xmod mounted and its mode set to external 3.3V (SW1 ON, SW2..4 OFF). Does TE0722 require a specific set of values on JTAG or UART pins from J2 connector on power-on to boot? I suppose Xmod doesn't apply any sequence on power-on there, and I don't see any other reason for Zynq to not start.
2. I've tried to short RESn pin (called NRST on schematic; applied to POR-circuit that feeds POR_B signal) to ground to issue a hardware reset without removing the supply, and Zynq doesn't seem to reboot in any configuration (Xmod powered or ext. supply). It either doesn't boot at all (red LED light lit) or doesn't work after boot (UART inaccessible). (update: I've checked it again, POR_B is working with Xmod applied, Zynq resets correctly; probably it was the issue with parasitic capacitance which didn't release the NRST signal)

These two questions are rather important as we are designing a carrier board now.

[netnazgul]

update2: TE0722 starts even without Xmod mounted, but takes a lot of time to be programmed (up to 15 seconds). Applying POR_B has the close to the same boot-up duration.

[JH]

With your own Boot.bin? Or did you use the prebuilt Boot.bin from the reference design?
Can you try with correct Boot.bin from Reference Design?
15 Second so see any output on console or PROG Done Pin is on (Red LED goes off)?

br
John

[netnazgul]

With your own Boot.bin? Or did you use the prebuilt Boot.bin from the reference design?
15 Second so see any output on console or PROG Done Pin is on (Red LED goes off)?

Tested on my customized FSBL BOOT.bin image made from reference design FSBL. I've added a simple PL block that controls RGB LED, and a loop function that switches CPU LED (connected to MIO7) and periodically outputs values to console. So I judge boot time as a time interval between applying supply and seeing PROG Done pin going off and CPU LED/RGB LED start blinking.
Another difference is I'm running CPU at 100MHz (because at 667MHz it heats up too much and I don't need such frequencies anyway).

Can you try with correct Boot.bin from Reference Design?

I've downloaded and flashed factory image (from here), with the same results - Red LED goes off after ~10 seconds. I can't check the console output because Xmod is not mounted in this test.

[JH]

Take this one:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0722/Reference_Design/2017.1/test_board

for TE0722-02I take:  test_board\prebuilt\boot_images\te0722_i\fsbl_app\BOOT.bin

br
John

[netnazgul]

Result is the same - starts quickly with Xmod mounted (doesn't matter whether it's connected to USB or not), takes a lot of time to boot without Xmod.

[JH]

Do you mean Boot from QSPI is faster, if you connect XMOD only?
Or compared to program over JTAG?
br
John

[netnazgul]

Yes, I'm comparing just flash boot, JTAG is not connected/used i.e. USB is not connected to Xmod, only V3.3/GND pins from TE0722 are connected to external supply.

[JH]

What did you use for power supply?

br
John

[netnazgul]

Keithley 2400. I've set up V-source as 3.3V, current compliance limit as 500mA. To check that it's not due to power-on current surge, I've set it as high as 1A, doesn't make a difference.
TE0722 drains ~75mA current when it's not yet booted (Red LED on), something around 180mA on a simple program after boot is complete and PL is programmed.

[JH]

Hi,
Normally, it shouldn't matter. There is only JTAG and UART connected. And if you set TE0790 DIP to ON OFF OFF OFF, TE0790 is also powered by your power supply.
I will check this with an TE0722 next week.
br
John

[netnazgul]

Actually now sometimes I get longer boot times even when Xmod is mounted, so I'm out of ideas. And it is quite strange if it only occurs on my board and wasn't the issue before.
It drains ~75mA (~88mA with Xmod) on power-on for several seconds, up to 15, then some kind of switch occurs, and normal operation is 180mA (190mA).

I'll try also to test for this behaviour on another TE0722 next week.

[netnazgul]

Ok, I've finally figured it out. The problem was indeed with power-on current surge, and it was current compliance auto-range setting on Keithley that prevented the device from starting up correctly. Once it's switched to manual, TE0722 boots up swiftly every time. 
Thank you for your patience. I'll continue on working with the device.