AXI design approach

[zaknahhas]

Hello all,

I am newbie in SOC design and I would ask about a design approach that I want to implement on the zynq Z-7010:

I already implemnted on the PL side a design which take some inputs and process it resulting a 32bit value. At some points I want to send trigger signals so the PL should store the current 32bit value fastly in the RAM letting the PS to process it whenever it wants.

I have readed a lot about the AXI interfacing but somehow I did't figure out the best way to send these values ... should I implement a "custom" AXI master module in PL Side ? should this module send the data to a DMA controller or through the PS  to the RAM ?

or there is a better way to handle this data transfer ?


Thank you in advance, I really appreciate it  !

[Oleksandr Kiyenko]

Hello,

Implementation depend on required bandwidth. If you need to send one 32bit value from time to time you need register interface. If you need to process data stream you need DMA interface.
Think that you should start from simple custom AXI core with registers.

Best regards
Olelsandr Kiyenko

[zaknahhas]

Hello @Oleksandr Kiyenko and thanks for your reply and time,

To clarify the design again, I become trigger signals for about 4 seconds in a frequency of 1MHz. at each trigger signal I should store the current 32bit so when this trigger-train ends, the Processor (PS) should begin to analyse these values (about 16MB) with no time constrains (5 to 10 seconds or more is not a problem).

I feel that my problem is that I could't figure out how to transfer my 4 byte (bare) data through AXI ... don't know if I have more than that

Do you have some example only diagram which illustrate it ?


Thanks a lot again for your time, and sorry for bothering you as a begginer

[Oleksandr Kiyenko]

Hello,

If you want to transfer some big amount of data you need to use PS Slave interface, (usually HP Slave). Then you can transfer data from your stream via "AXI Datamover" core to DDR memory.


Best regards
Oleksandr Kiyenko