Author Topic: ArduZynq Boot Modes  (Read 5278 times)

DaveSB55

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ArduZynq Boot Modes
« on: October 08, 2016, 05:47:33 PM »
Looking at the schematic for the TE0723-02M, MIO2, MIO3, MIO4 and MIO5 are all pulled down to Gnd, which would seem to imply that the module is always configured for JTAG (Cascaded) boot.

Am I missing something that lets me boot from QSPI or SD Card?

Thanks

DaveB

Antti Lukats

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Re: ArduZynq Boot Modes
« Reply #1 on: October 10, 2016, 11:22:04 AM »
Zynq 7010 in CLG225 does not support direct SD Card boot mode so bootmode is strapped to SPI flash boot. Only FSBL needs to be in Flash, the remaing can be loaded from SD Card.
JTAG boot is always possible no matter the boot mode setting.

DaveSB55

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Re: ArduZynq Boot Modes
« Reply #2 on: October 10, 2016, 07:28:32 PM »
Hmmm,

I had assumed QSPI would work and tried it and got no output on the serial port (unlike when JTAG programmed) - whereas I had no problem with a microZed board set to boot to QSPI.

I am still confused by the schematic that seems to pull all the boot mode lines down to 0 which is not QSPI booting.

Am I missing something here?

Thanks

DaveB

JH

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Re: ArduZynq Boot Modes
« Reply #3 on: October 10, 2016, 08:22:00 PM »
Hi,

did you mean the following schematic(page4):http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0723/REV02/Documents/SCH-TE0723-02M.PDF
MIO5 is set to 3.3V with pullup. MIO2,3 and4 is GND, so QSPI with JTAG cascade is select. See UG585 Boot Mode MIO Strapping Pins.

br
John

DaveSB55

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Re: ArduZynq Boot Modes
« Reply #4 on: October 10, 2016, 09:04:42 PM »
Hmm, yes, it is, I know I am Dyslexic, but even for me not seeing the 3.3V pull-up is a tad brain dead, sorry

That said, I followed a simple sequence

1) Hello World via JTAG
2) Hello World via FSBL and QSPI

1) Worked, 2) didn't hence my original question

Deleted all the SDK projects and started again and now even 1) (JTAG) isn't working, this is starting to look ominous :-(

JH

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Re: ArduZynq Boot Modes
« Reply #5 on: October 11, 2016, 08:10:50 AM »
Hi,

can you test it with the prebuilt file from the reference project:https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/TE0723/Reference_Design/2016.2/test_board
UART0 over FPGA-Fabric is used for Serial link over JTAG-USB.
And "Hello World" appears only one time after start, so you must open the serial link and reboot the device with S1 Button or via Vivado.

br
John

DaveSB55

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Re: ArduZynq Boot Modes
« Reply #6 on: October 11, 2016, 09:00:51 AM »
Ok, will do, I am away from my office until Wednesday evening so will try then.

Thanks

DaveB

DaveSB55

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Re: ArduZynq Boot Modes
« Reply #7 on: October 13, 2016, 06:32:14 PM »
Hmm, that image works but it is from a later reference project than the one I found on the trenz website (which was for an earlier version of Vivado, not the 2016.2 I'm running), so maybe despite being able to JTAG an image once, there was something else going on.

At the weekend I'll use the 2016.2 files to create a new SDK, bsp, fsbl and test program and see how I get on.

Thanks for the link for the new reference project.

DaveB

DaveSB55

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Re: ArduZynq Boot Modes
« Reply #8 on: October 13, 2016, 07:53:15 PM »
Ok, I suspect my problem is that I want to set up things from scratch by hand and at the Vivado step I just create a Zynq processor as I did for the microZed, but I don't add anything for UART_0 to route via the FPGA. That is I only have external connections for DDR and FIXED_IO.

I'm very much a beginner using FPGA tools, it's not obvious to me how, having my Block Design, I add an output for UART0 - is this simple to do and where should I look for documentation on doing it?

Sorry to be a nuisance, I'm a S/W developer trying to get his head around FPGA and it's a steep learning curve!

DaveB
« Last Edit: October 14, 2016, 09:43:45 AM by DaveSB55 »

JH

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Re: ArduZynq Boot Modes
« Reply #9 on: October 14, 2016, 09:47:10 AM »
Hi,
no problem. To work with FPGA thirst time is not so easy. At beginning you can use our reference design and/or board part file (initial all PCB specific setting for zynq-ps).
For 2016.2 are also a prebuilt Boot.bin with Hello-World available, located in the subfolder prebuilt/boot_images/<your device>/hello_world
It's in the larger Download file: http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/TE0723/Reference_Design/2016.2/test_board/te0723-test_board-vivado_2016.2-build_07_20161007102438.zip

We have some descriptions but for basic you must use Xilinx  documentation and tutorials.
Here are some Links (Xilinx documents are also referenced there):
Some Descriptions to Xilinx Doku, Vivado+Board Parts,SDK and SDSOC: https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264




br
John


DaveSB55

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Re: ArduZynq Boot Modes
« Reply #11 on: October 15, 2016, 09:52:29 AM »
Ok,

1) I replaced the FPGA image I was using (generated by my copy of Vivado) with the one in the test_board:

test_board\prebuilt\hardware\te0723_02m\test_board.bit

That "solves" the serial port problem and I can see output from "Hello World" when booting from QSPI

2) However since my primary task at the moment is to debug a modified version of the FSBL (First Stage Bootloader), I don't have Serial Output until after the FPGA has been loaded (I enabled FSBL_DEBUG_INFO) because, I think, pushing the "reset" button clears the FPGA and until the FSBL has reloaded it, I have no serial port, so the output I see on the serial port after pushing reset is:

▒▒▒▒▒▒(▒*
         /'&L&&N'HL▒▒FFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
...

3) Does that seem like a reasonable conclusion? If so, I can't do what I need to do with the Arduzynq as I need console output from the start of the FSBL :-(

DaveB

Antti Lukats

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Re: ArduZynq Boot Modes
« Reply #12 on: October 15, 2016, 10:46:21 AM »
Hi

there are compromises to be taken, bei arduzynq is the usb uart on PL EMIO, so you can not really debug FSBL using it, we did it so as we wanted to connect FTDI with FIFO mode support.

there is another MIO UART available on pin header, so that could be used for FSBL debug, or:

you can use ARM DCC over JTAG for FSBL debug then you see the debug messages in the SDK debug window, this will work, just select the jtag uart in fsbl BSP


DaveSB55

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Re: ArduZynq Boot Modes
« Reply #13 on: October 15, 2016, 01:23:04 PM »
Hi,

Yes I understand, it is my confusion over your design, I feel I understand better now and will go away and explore ways of achieving what I want to.

If you can help clear up another confusion please.

The Arduzynq has the form factor of an Arduino, however I suspect it's I/O is not 5V tolerant - is that correct? How do you envision it being used - as a primary board with (3V3) shields attached, as a shield on top of which Arduino family? Neither?

Thanks for your patience

DaveB

Antti Lukats

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Re: ArduZynq Boot Modes
« Reply #14 on: October 17, 2016, 02:27:35 PM »
There are many many other Arduino boards that do not have 3.3V tolerant I/O.

We opted to not use level shifter to have direct access to FPGA that is more flexible.