TE0720_L1IF SDK debug fails: 3.. MPCore #1 (DEVICEEN is '0')

[timholt]

Hi,  I am a software engineer switching from MicroZed and Myir Zynq 7020 boards to use Trenz TE0720 boards for our final design.  We will use TE0720-03-1QF in our final PCB design, but while I am able to load and run with UART output directly into DDR on other boards get a DEVICEEN signal is zero indication on the second core #1.   I am not finding I can load a program into DDR memory space with Xilinx SDK 2016.2 on the TE0720-03-L1IF board combined with TE0701-05 carrier board.    I am able to program SPI flash and boot and run from it.  Just thought I  would post this here in case there is a known issue.  The only place I have found where Device Enable in the APB registers (DEVICEEN) as zero is in a case where somebody had a bad custom PCB.  I am presuming that the ps7_init.tcl has something wrong in it. But do not see how something like having 512Kb DRAM versus 1GB would break things for the second core.
Thanks
Tim

[Antti Lukats]

Hi

I am curious about the DEVICEEN bit you are mention, you say it is related to bad custom PCB, where this statement is coming? What Xilinx document?

We occasionally see debug issue on different Zynq platforms, but never constantly DEVICEEN as much as I recall.

We do most testing and debug if needed on modules with 1GB DDR installed, but as long you you correct FSBL/TCL for 512K version all must work with less memory too.

[timholt]

Thanks Antti.  It is good to know that this has not been seen there before.   It is indicated for the second A9 core #1 versus #0.  I agree the lower 512Mb should be OK. But I have just received more boards that TE720-03-1CF along with TE703-05 carrier boards for the team.  I will setup the JTAG and and work with these.  I do not think we will ever use 1Gb but we have decided to use those.   I may reexamine the -Lf1F board later but more likely will just move on.
Thanks!

[timholt]

Hi Antti,
     The 3 TE0720--0-ICF and 3 TE0703-03 boards came today and I am able to load the FreeRTOS Zynq example and run it using the SDK (UDP debug is working but I need to remap the UART I think which is OK).  I will not worry about the 512Mb board for now.  The documentation on the TE0703 is old but I needed to power the FPGA banks to 3.3V using the jumpers A-D.   I suspect this level may be needed for JTAG or the AP (debug register is returned as a zero value). 
Thanks
Tim

[Antti Lukats]

Hi

no, the IO voltages or lack of them should have no impact at all on PS or ARM debug.

[timholt]

Yes.  Thanks. I was mistaken.  The JTAG is working fine with the 1.8V jumpers.