TE0720 PHY config

[kmbm]

Hi, I have a problem with my dts in petalinux 2014.4 I'd like to use eth0 and uart1. What can be wrong. only gpio works fine. I will be gratefull for any sugestions

My dts file:

/dts-v1/;
/include/ "zynq-7000.dtsi"
/include/ "pl.dtsi"
/ {
   cpus {
      cpu@0 {
         operating-points = <666666 1000000 333333 1000000>;
      };
   };
   chosen {
      bootargs = "console=ttyPS0,115200";
   };
   aliases {
      ethernet0 = &gem0;   
      serial0 = &uart0;
      serial1 = &uart1;
      
   };
   memory {
      device_type = "memory";
      reg = <0x0 0x40000000>;
   };
};
&gem0 {
   local-mac-address = [00 0a 35 00 00 02];
   phy-mode = "rgmii-id";
   status = "okay";
   xlnx,ptp-enet-clock = <0x69f6bcb>;
   phy-handle=<&phy0>;
   mdio{
   #address-cells=<1>;
   #size-cells=<0>;
      phy0:phy@0{
      compatible="marvel,88e1512";
      device_type="ethernet-phy";
      reg=<0>;
      };
   };
};
&gpio0 {
   emio-gpio-width = <64>;
   gpio-mask-high = <0x0>;
   gpio-mask-low = <0x5600>;
};

&uart0 {
   current-speed = <115200>;
   device_type = "serial";
   port-number = <0>;
   status = "okay";
   reg = <0xe0000000 0xe0000>;
   interrupts = <0 27 4>;
   interrupt-parrent = <&intc>;   
};
&uart1 {
   current-speed = <115200>;
   device_type = "serial";
   port-number = <1>;
   status = "okay";
   reg = <0xe0001000 0x1000>;
   interrupts = <0 50 4>;
   interrupt-parrent = <&intc>;   
};









Xilinx First Stage Boot Loader
Release 2015.3  Feb  3 2016-10:44:04
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 4
Partition Number: 1
Header Dump
Image Word Len: 0x000F6EC0
Data Word Len: 0x000F6EC0
Partition Word Len:0x000F6EC0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD14B7E
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00002A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0
PCAP DMA DEST LEN 0xF8007024: 0x000F6EC0
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00010B8B
Data Word Len: 0x00010B8B
Partition Word Len:0x00010B8B
Load Addr: 0x3FC00000
Exec Addr: 0x3FC00000
Partition Start: 0x000FD490
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0x806D065D
Application
Partition Number: 3
Header Dump
Image Word Len: 0x00000D92
Data Word Len: 0x00000D92
Partition Word Len:0x00000D92
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x0010E020
Partition Attr: 0x00000011
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFEEF4A7
Application
Handoff Address: 0x3FC00000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1
Booting Linux on physical CPU 0x0
Linux version 3.17.0-xilinx (root@ubuntu) (gcc version 4.8.3 201                                                                             40320 (prerelease) (Sourcery CodeBench Lite 2014.05-23) ) #19 SMP PREEMPT Mon Fe                                                                             b 15 09:47:09 CET 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: xlnx,zynq-7000
cma: Reserved 128 MiB at 38000000
Memory policy: Data cache writealloc
PERCPU: Embedded 8 pages/cpu @7779c000 s8704 r8192 d15872 u32768
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260096
Kernel command line: console=ttyPS0,115200
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Memory: 897700K/1048576K available (4710K kernel code, 240K rwdata, 1628K rodata                                                                             , 3588K init, 214K bss, 150876K reserved, 0K highmem)
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xffe00000   (2048 kB)
    vmalloc : 0x80800000 - 0xff000000   (2024 MB)
    lowmem  : 0x40000000 - 0x80000000   (1024 MB)
    pkmap   : 0x3fe00000 - 0x40000000   (   2 MB)
    modules : 0x3f000000 - 0x3fe00000   (  14 MB)
      .text : 0x40008000 - 0x40638d38   (6340 kB)
      .init : 0x40639000 - 0x409ba200   (3589 kB)
      .data : 0x409bc000 - 0x409f80e0   ( 241 kB)
       .bss : 0x409f80e0 - 0x40a2da2c   ( 215 kB)
Preemptible hierarchical RCU implementation.
        Dump stacks of tasks blocking RCU-preempt GP.
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS:16 nr_irqs:16 16
L2C: platform provided aux values match the hardware, so have no effect.  Please                                                                              remove them.
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76360001
slcr mapped to 80804000
zynq_clock_init: clkc starts at 80804100
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 3298534883328ns
timer #0 at 80806000, irq=43
Console: colour dummy device 80x30
Calibrating delay loop... 1332.01 BogoMIPS (lpj=6660096)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
CPU: Testing write buffer coherency: ok
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x473e10 - 0x473e68
CPU1: Booted secondary processor
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
Brought up 2 CPUs
SMP: Total of 2 processors activated.
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
regulator-dummy: no parameters
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
cpuidle: using governor ladder
cpuidle: using governor menu
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0x80880000
VCCPINT: 1000 mV
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
media: Linux media interface: v0.10
Linux video capture interface: v2.00
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@l                                                                             inux.it>
PTP clock support registered
EDAC MC: Ver: 3.0.0
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arm_global_timer
NET: Registered protocol family 2
TCP established hash table entries: 8192 (order: 3, 32768 bytes)
TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP: reno registered
UDP hash table entries: 512 (order: 2, 16384 bytes)
UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
futex hash table entries: 512 (order: 3, 32768 bytes)
jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
msgmni has been set to 2009
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-2364208
dma-pl330 f8003000.dmac:        DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Even                                                                             ts-16
e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 59, base_baud = 3125000) is a                                                                              xuartps
console [ttyPS0] enabled
e0001000.serial: ttyPS1 at MMIO 0xe0001000 (irq = 82, base_baud = 3125000) is a                                                                              xuartps
xdevcfg f8007000.devcfg: ioremap 0xf8007000 to 8086c000
[drm] Initialized drm 1.1.0 20060810
brd: module loaded
loop: module loaded
CAN device driver interface
e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
xilinx_emaclite 40e00000.ethernet: Device Tree Probing
xilinx_emaclite 40e00000.ethernet: no IRQ found
xilinx_emaclite 40e10000.ethernet: Device Tree Probing
xilinx_emaclite 40e10000.ethernet: no IRQ found
libphy: XEMACPS mii bus: probed
xemacps e000b000.ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
i2c /dev entries driver
cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at 80870000 with timeout 10s
zynq-edac f8006000.memory-controller: ecc not enabled
Xilinx Zynq CpuIdle Driver started
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
sdhci-pltfm: SDHCI platform and OF driver helper
ledtrig-cpu: registered to indicate activity on CPUs
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
TCP: cubic registered
NET: Registered protocol family 17
can: controller area network core (rev 20120528 abi 9)
NET: Registered protocol family 29
can: raw protocol (rev 20120528)
can: broadcast manager protocol (rev 20120528 t)
can: netlink gateway (rev 20130117) max_hops=1
Registering SWP/SWPB emulation handler
/opt/pkg/petalinux-v2014.4-final/components/linux-kernel/xlnx-3.17/drivers/rtc/h                                                                             ctosys.c: unable to open rtc device (rtc0)
ALSA device list:
  No soundcards found.
Freeing unused kernel memory: 3588K (40639000 - 409ba000)
INIT: version 2.88 booting
Creating /dev/flash/* device nodes
random: dd urandom read with 0 bits of entropy available
starting Busybox inet Daemon: inetd... done.
Starting uWeb server:
NET: Registered protocol family 10
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
Removing any system startup links for run-postinsts ...
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.22.1) started
Sending discover...
Sending discover...
Sending discover...
No lease, forking to background
done.

[Antti Lukats]

so what is wrong? you something is wrong but what?

[kmbm]

if I try echo 'abc' >  /dev/ttyPS0 -> OK    echo 'abc > /dev/ttyPS1 - no response
and i can't connect with ethernet ifconfig eth0 192.168.0.1 but connection is failed

[Antti Lukats]

Lets try 1 by 1, the UART issue first

how did you configure UART1 in Vivado?

to MIO?
to EMIO?

did you do the all the flow? vivado bitgen, export hdf, import hdf in petalinux?


to where did you connect your second terminal?

[kmbm]

I've routed UART1 to EMIO and then to PMOD connector. The uart1 will be connected to the rs232<->rs485 converter but now I'd like to check only rs232.

All the steps: vivado bitgen, export and import hdf i've already done

[Antti Lukats]

there can be several places where problem can be.

Generic UART troubleshooting:

1) check that the external terminal works, take the the pmod out, and place loopback there and check you see the echo back
2) make TXD <= RXD; in FPGA and verify that the ECHO works

then you know that hardware wise you have the terminal ok, and the pin mapping and ALL wiring OK

3) use LED to show the active states of the EMIO UART RXD TXD (or chipscope)

[kmbm]

Ok, the problem can be in vhd. My vhd code:

entity zynq_sys_wrapper is
  port (
  ....
  UART_1_rxd : in STD_LOGIC;
  UART_1_txd : out STD_LOGIC
  }

architecture STRUCTURE of zynq_sys_wrapper is
  component zynq_sys is
  port (
  ...
  uart_1_rxd : in STD_LOGIC;
  uart_1_txd : out STD_LOGIC;
}



xdc file:

set_property PACKAGE_PIN AA19 [get_ports UART_1_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_rxd]

set_property PACKAGE_PIN AA18 [get_ports UART_1_txd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_1_txd]





is it OK? On the schematic I've made uart port external.

I'm doing it first time so there can be unexpected mistakes . And my question is how to correctly write top.vhd?

[Antti Lukats]

if you want to use PS UART via EMIO then you do not need to write or modify any VHDL code. There is no need for it at all.

What I suggested to test that the IO and connector and wiring is correct:

1 you make empty top.vhd with NO ZYNQ PS
2 you write one line in the body

TXD <= RXD;

and you test this for terminal echo

if that works you know your hardware works.

[kmbm]

There is a problem with echo. I've no response. I think i made a mistake with signal's connection

When I connect UART_1_rxd and txd to the pins in xdc I have an error uart_1_rxd has no default value (in top.vhd)

[Antti Lukats]

I am sorry I do not follow you any more.

I suggested for testing implementing a single wire in VHDL. here is the complete code:
=================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is Port ( RXD  : in   STD_LOGIC; TXD  : out  STD_LOGIC  );
end top;

architecture Behavioral of top is
begin
   TXD <= RXD;
end Behavioral;
=======================================================

use this code, set XDC as required, load FPGA over jtag and type something on your terminal, if you see echo then you are ok. if not then either XDC or cables are wrong.

[kmbm]

Thanks a lot for your help.

I know that I am very disruptive, but I have a last question.
I checked everything and the vivado schematic is OK- it works

The problem is with my linux and configuration. In config file which is generated automatically I have unset uart1_select...

#
# Serial Settings
#
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_9600 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_19200 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_38400 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_57600 is not set
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_115200=y
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_230400 is not set

How to config petalinux to enable CONFIG_SUBSYSTEM_SERIAL_PS7_UART_1_SELECT = y.

[Antti Lukats]

Hallo,

there should REALLY be no reason to-do such hard modding of petalinux, you should not modify those files..!

https://wiki.trenz-electronic.de/display/PD/Petalinux+KICKstart

there are 3 user editable files.

So whatever you do, you either use the menu-config or modify those files