TE0712 with TE701 - xdc IOSTANDARD setting for signals connected to FMC

[socmp]

Hi,

I am trying to connect some differential signals in my design to FPGA pins which are in turn connected to FMC connectors via SoM (TE0712) to carrier (TE0701), for example (FPGA pins C20, D20, B20, A20, F18, E18, C22, B22 etc) which are marked in board part file as iostandard="LVCMOS33".

But, Vivado specifically asks for a differential IOSTANDARD. This design is being ported from a Kintex7 device family (ISE) to Artix7 in TE0712 SoM; IOSTANDARD used in that Kintex7's working UCF file is IOSTANDARD=LVDS_25. I tried LVDS_25 but Vivado does not recognize them. Any suggestions would be helpful.

Thanks in advance.

[Oleksandr Kiyenko]

Hello,

Xilinx FPGA not support mixing LVDS_25 and LVCMOS33 in same FPGA bank. So if you need to work with differential signals you need:
1) Set LVDS_25 to differential signals you need. All this signals should have differential buffer instance!
2) All other signals from this bank should have LVCMOS25
3) FMC_VADJ should be configurewd to 2.5V

Best regards
Oleksandr Kiyenko

[Antti Lukats]

Hi,

I am trying to connect some differential signals in my design to FPGA pins which are in turn connected to FMC connectors via SoM (TE0712) to carrier (TE0701), for example (FPGA pins C20, D20, B20, A20, F18, E18, C22, B22 etc) which are marked in board part file as iostandard="LVCMOS33".

But, Vivado specifically asks for a differential IOSTANDARD. This design is being ported from a Kintex7 device family (ISE) to Artix7 in TE0712 SoM; IOSTANDARD used in that Kintex7's working UCF file is IOSTANDARD=LVDS_25. I tried LVDS_25 but Vivado does not recognize them. Any suggestions would be helpful.

Thanks in advance.

1) it is needed to use LVDS_25 or LVDS depending if the bank is HR or HP. This makes lots of confusions - the LVDS and LVDS_25 for 7 series are THE SAME just for different  type of IO bank.
2) LVDS input is possible in IO bank with 3.3V supply if differential interm is not used. LVDS outputs in HR banks turn OFF hard when VCCIO is too high, this is some small xilinx secrets. So if you try to outsmart and select LVDS 2.5V standard and have VCCIO 3.3V  then the LVDS output would be DRIVEN to LOW fixed.