TE0720 Ethernet IP Configuration Failed

[Tim S.]

Dear Antti Lukatz and Community,

I am using Trenz Ref. Petalinux 2014.4 for my TE0720 board. After booting linux on my board and logging into, I am unable to configure the eth0 ip configuration.

Commonly I am using the command Xilinx described in its PDF Tutorial "Petalinux Getting Startet": $ifconfig eth0 192.168.10.10

This command throws me an error message as you can see in attached jpg-file. ('eth0_error_message.jpg')
In addition I uploaded another picture about showing a failed PHY init before reaching U-Boot. ('phy_init_failed.jpg')

Does anybody know how to solve this error and subsequently how to configure the eth0 IP?

For your information:

I found 2 solutions for solving this problem in a topic in Xilinx Forum. I tried both but they do not work. http://forums.xilinx.com/t5/Embedded-Linux/xemacps-e000b000-ps7-ethernet-eth0-no-PHY-setup/td-p/499018

Best regards

Tim

[Oleksandr Kiyenko]

Dear Tim,
Your bootlog show 2 problems
- MII probe fail
and as result of first problem
- No PHY found

To solve it you should check:
- MDIO configuration for Ethernet in your Vivado project
- FSBL configuration (read MAC address and patch PHY settings)
- u-boot ethernet configuration

Best regards
Oleksandr Kiyenko

[Tim S.]

Thanks for your reply. I have checked your mentioned steps and figured out that the problem was caused by FSBL configuration.

To create a BOOT.bin with petalinux tools, I have taken fsbl.elf file, which I created in SDK. This fsbl.elf file was build with 'Debug' mode configuration. After I changed the mode in build configuration to 'Release', I used the newly generated fsbl.elf file in petalinux tools and it worked. Now, in bootlog PHY is detected and ethernet connection can be configured in Linux.

Best regards

Tim S.

[Antti Lukats]

thats a bit strange, but good point

usually the debug versions also works, but maybe there are cases where it makes difference thank you for finding and reporting it, we can watch more closely this then to see if it makes problems if the fsbl is compiled as debug and not release

[bgrissom]

I ran into this same problem.  My solution is much more like the Xilinx post referenced above.  I had originally ran into this problem with the Zedboard and found that the Zedboard BSP had a .dts file that I used for reference:

Avnet-Digilent-ZedBoard-2014.4/subsystems/linux/configs/device-tree/system-top.dts

So from that file, I added the following to subsystems/linux/configs/device-tree/system-top.dts

&gem0 {
    phy-handle = <&phy0>;
    ps7_ethernet_0_mdio: mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        } ;
    } ;
}; 

Then rebuild via "petalinux-build" and you're good to go.

--Brad