TE0630 and Memory Interface Generator

[towo]

Hello,

I am not that experienced with FPGAs but currently I'm working with a Spartan 6 on the Trenz TE0630.
I was trying to communicate with the DDR3-SDRAM via Memory Interface Generator.
The tesbench generated by the isim.bat works well and even the ise_flow.bat from the example design finishes with no errors.
But when executing the ise_flow.bat from the user_design, there is an error message, telling that the .ncd-file wasn't found:

ERROR:Bitgen:4 - The input NCD file "DDR3.ncd" is not in the specified location.

Looking at the ise_flow_results.txt, there is the following error message:

ERROR:Place:1205 - This design contains a global buffer instance,
   <memc1_infrastructure_inst/U_BUFG_CLK0>, driving the net, <c1_clk0_OBUF>,
   that is driving the following (first 30) non-clock load pins off chip.
   < PIN: c1_clk0.O; >

Followed by the recommendation for overriding this error by modifying the .ucf-file with:

PIN "memc1_infrastructure_inst/U_BUFG_CLK0.O" CLOCK_DEDICATED_ROUTE = FALSE;

After doing that, the ise_flow.bat runs perfectly and generates the .bit-file, but the memory ist not still working. When looking at the c1_calib_done-signal, it stays low.
What is the cause of that error and what am I apparently doing wrong?

Best regards

[Oleksandr Kiyenko]

Hello,

Unfortunately we don't have complete MIG reference project for this board. You can take paramethers for MIG from https://github.com/Trenz-Electronic/TE063X-Reference-Designs/blob/master/reference-TE0630/system.mhs
Usually such project do not require CLOCK_DEDICATED_ROUTE = FALSE constraints as have all clock input pins at GCLK pins. Please check your UCF file it should look like commented part at the end of https://github.com/Trenz-Electronic/TE063X-Reference-Designs/blob/master/reference-TE0630/data/system.ucf

Best regards
Oleksandr Kiyenko