TEI0006 clock synthetizer configuration

[guirenaud]

Hello

I'll use the TEI006 SOM with custom mother board
I'd like to change the default clock synthetizer configuration.
I'd like to have on OUT2 a 40MHz LVDS output. By default it outputs 100MHz LVCMOS (signals CLK2_P and CLK2_N from schematics SCH-TEI0006-04-API23A.pdf)
Is it possible ?
I'd like to be able to order the SOM with that config. by default.
We have already ordered one, can we update it also by ourself ? Which procedure should we use ?

Sincerely

[Antti Lukats]

please contact support email. A custom version of the CPLD firmware is needed to have different clocks.