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LEDs on TE0701 + TE0720

Started by eddydw, September 30, 2025, 06:17:54 PM

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eddydw

Hi ,

Is there a clear description of the LED status on the TE0701 + TE0720.

When I power the board there is a green led on the base board always on D22 and a RED Flashing led on the 0720 module . This is when J16 is placed.

Where can I find the detailed description of the leds and what they represent when continuously lighted or flashing?


I have no output from the UART when debugging a simple hello world bare metal application too?
I am stuck.
Thanks for a quick response


eddydw

Apparently, nobody is responding.

On the TE0701 led D22 is the power led indicating that the 3v3 supply is available on the te0720 module.
There are however 8 red leds D1,...D8 which are directly driven by the CPLD but also have a meaning? Where is the description of their meaning.


Wen power cycle the TE0701-06 with TE0720-04 without SD CARD inserted only D5 user led is red if I insert the SDCARD and power cycle then none of the user leds D1..D8 are on.

(BTW : there is also a RED LED blinking on the TE0720-04 module)

In this case which boot mode is then active?


MA

Hi and sorry for the late response,

you can find the description of the LEDs in the following documents


Green LED D22 'ON' on base board indicates available 3.3V voltage level of attached module.

The description of D1-D8 can be found in Port Description of TE0701 CPLD
  • ULED1: Displays the UART1 RXD signal
  • ULED2: Displays the UART1 TXD signal
  • ULED3: Displays the PGOOD signal status
  • ULED4: Displays the NOSEQ signal status
  • ULED5: Displays the boot mode state, if ON → JTAG boot mode
  • ULED6: Displays the boot mode state, if ON → eMMC boot mode
  • ULED7: Displays the boot mode state, if ON → SD card boot mode
  • ULED8: Displays the boot mode state, if ON → QSPI boot mode

For flashing Red LED, there are several LED Status Codes as described in TE0720 CPLD documentation.

Can you please
  • check, if you 'see' the FPGA in Hardware Manager
  • check the adjusted boot mode
  • check the level of adjusted FMC_VADJ
  • check the status of LED1 (D2) and LED3 (D4) on TE0720

Thanks and best regards,
Manuela

eddydw

Hi Manuela,

I have set SW4 and SW3 as follows :

S4[4..1] = [OFF,OFF,OFF,OFF]
SW3[4..1] =  [OFF,ON,OFF,ON]

Question 1 : According to the TRM-TE0701 pdf table on page 24  this means that VID2,VID1,VID0 are 000 and this FMCVADJ is 3.3V correct?

Since S4-4 (CM2) = OFF ==> PGOOD = 1

When SDCARD is inserted MODE = 0
==> Boot Mode = SD card Mode since PFOOD=1 and MODE=0 (according to https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD#TE0701CPLD-PCBREV06)
However there is a note (on page 24) that says "SC CPLD settings will be overridden by DIP switch S4, if one of them is set to one (OFF position)"

Question : Does this mean that OFF = 1 and ON=0 ?

The table on page 25 is very confusing.


Bottom line : We would like to be able to boot from SDCARD and also see the UART output on a terminal. The MIO14 and MIO15 pins are connected to the FTDI IC. The documentation refers to UART1 on the Zynq 7020,but that is wrong. It is actually UART0!
I have changed the UART from UART1 to UART 0 in the reference design but we still cannot see anything on the UART terminal too (by using a simple Hello World baremetal application),so we suspect that there is still a missing setting.


We would appreciate it if you could give us the settings of the DIP SWITCHES S3 and S4 and other neccesary settings (like for example JUMPERS) on the TE0701 carrier board in order to be able to boot from SDCARD and to be able to see the UART to.


I have created a bootable SDCARD Image with petalinux. I want to test it but I need to have a working UART,but since there is still no output on the UART I am blocked as the UART terminal is needed to view the logging of the boot process.


Please help? We have been stuck for a few weeks.
Can we eventually have a direct contact by gorkys@telenet.be



JH

Hi,
regarding VADJ voltage:
S4 DIP is inverted in case it's ON position it will set VIDx to zero. See Schematics page 17
for 3.3V set  S4-1 ON, S4-2 ON S4-3 ON
On the DIP switch section you see the DIP position
https://wiki.trenz.local/display/PD/TE0701+TRM#TE0701TRM-ConfigurationDIP-switches
Or page 30 in the PDF
I will add a note to the CPLD Pin description on the TRM to make it more clear there and refer to there to the DIP setting.

To supply  bank voltages with generated VADJ voltage check also Jumper on J17 and J16 and J21:
https://wiki.trenz.local/display/PD/TE0701+TRM#TE0701TRM-SummaryofVCCIOconfigurationviajumpers
or current pdf page 36/37

Regarding Boot mode.
S3 DIP is also inverted (ON set signal to GND).


So for SD Boot mode set
S4-4 (CM2) to OFF and insert SD Card with fat32 partition. Files from the current reference design see:
https://forum.trenz-electronic.de/index.php/topic,2856.0.html


Regarding S3 DIP
S3-1(CM1) OFF --> Standard Power sequencing: https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD#TE0701CPLD-NOSEQ
S3-2 OFF --> don't care on TE0701-06(current revision), will be used in the next revision to get access to module CPLD
S3-3 ON --> JTAG is connected to the module FPGA https://wiki.trenz-electronic.de/display/PD/TE0701+CPLD#TE0701CPLD-JTAG
S3-4 OFF --> Don't care it controls MIO0 signal of the carrier

Regarding UART,
you are right for TE0720 module MIO 14/15 is UART0 in PS configuration. The problem is that the carrier is for different modules. Therefore, uart0 does not refer to the controller of the TE0720. It's general number only on this documentation.  Important is the Pin connection, we use always JB1-91(JM1-92) and JB1-86(JM1-85) for UART on our reference designs together with our carriers, see:
https://wiki.trenz-electronic.de/display/PD/4+x+5+SoM+Integration+Guide#id-4x5SoMIntegrationGuide-ModulePinoutOverview

So please try out our reference design at first.

br

John