sys_clk IOSTANDARD for TE0714

[bggardner]

According to SCH-TE0714-04-42I-7-B.PDF, the 25MHz oscillator (U8) is powered by 1.8V.  The oscillator output is connected to B14_L13_P on Bank 14 (sys_clk in the board file), which is powered by VCCIO_0.  R21 connects VCCIO_0 to 3.3V, thereby making the IOSTANDARD for Bank 14 LVCMOS33.  However, LVCMOSS33 requires a minimum input-high voltage of 2.000V per AMD DS181, which the 1.8V-driven oscillator is unable to supply.  The TE0714_35_2I board file specifies sys_clk having IOSTANDARD LVCMOS33.  Is this an error with the schematic or otherwise unintended?

[Antti Lukats]

It is documentation XDC issue, please select SSTL18_I as IO Standard, after that you need open device constraints windows and use mouse to drop the IO Bank 14 to "0.9V" this will enable internal VREF.

Then it should work.

[bggardner]

Thank you.  The sys_clk input (somehow) still works using LVCMOS33, but also works with your suggested changes.  For the benefit of others, I replaced

set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports sys_clk]

with

set_property INTERNAL_VREF 0.9 [get_iobanks 14]
set_property -dict {PACKAGE_PIN T14 IOSTANDARD SSTL18_I} [get_ports sys_clk]