Virtual FIFO Controller with MIG (TE0600 GigaBee)

[mrb]

Hello,

i want to buffer 32bit data from axi4 stream into DDR3 RAM bevor sending over UDP/IP. My intention is to use the virtual FIFO controller for this because it has an axi interface to the MIG. (i want to build my complete project in ISE and without microblaze)

As i read in previous posts about the MIG i can't use the MIG reference project from the Trenz website as finished module because it's not tested and only made to set the pin layout. It also has not the axi4 interface that i need.

Can you tell me what settings i have to make by creating a MIG core myself by the wizard and what ports and how many ports i have to use (i suppose one write and one read port, both 32bit)? Do i have to use the ucf file from the reference project (or at least compare them)?

My component declaration of the virtual fifo (signals commented in german):

Code Select Expand


-- component declaration of vfifo
component vfifo
port(
------ Generelle Signale ---------------------------------------------
aclk : IN STD_LOGIC; -- AXI clk für Ein- und Ausgang
aresetn : IN STD_LOGIC; -- asynchroner reset (kommt aber synchron aus reset (intern sichergestellt))

------ Signale zum MIG -----------------------------------------------
-- write adress channel
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- channel identifier (Ziel als Routing Information)
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Write Adresse (erste Adresse Burst Zyklus)
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Länge des Burst Zyklus (genaue Anzahl)
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- Burst Größe (größe jedes Transfers im Burstzyklus; hängt von der Datenbreite ab)
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Art des Burst; immer gesetzt auf inkrementierte Transfer
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Lock Type; immer 0
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Cache Typ; immer 0
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- Protection type; immer 0
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Quality of Service; immer 0
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Region Identifier; immer 0
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Write Adress Channel User; immer 0
m_axi_awvalid : OUT STD_LOGIC; -- Write Adress Valid; Angabe, ob gültige Write Adress- und Kontrollinformationen verfügbar sind (1 = valid)
m_axi_awready : IN STD_LOGIC; -- Write Adress Ready; zeigt an, ob der Slave bereit ist eine Adresse zu empfangen

-- write channel Signale
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Write Daten
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Write Strobes; ??? (S.19)
m_axi_wlast : OUT STD_LOGIC; -- zeigt den letzten Transfer in einem Burst Zyklus an
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Write Data Channel User; immer 0
m_axi_wvalid : OUT STD_LOGIC; -- Write Valid; ob Lesedaten verfügbar sind (1 = Write-Daten und Strobes sind verfügbar)
m_axi_wready : IN STD_LOGIC; -- Write Ready; ob Slave bereit ist Daten zu aktzeptieren (1 = Slave bereit)

-- Write Response Channel Signale
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- Antwort ID...
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Write Response; Status des Schreibevorgangs (erlaubt sind: OKAY,EXOKAY,SLVERR,DECERR)
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- ungenutzt im VFIFO (Benutzersignal)
m_axi_bvalid : IN STD_LOGIC; -- Write Response Valid - zeigt an, ob eine gültige Schreibantwort verfügbar ist
m_axi_bready : OUT STD_LOGIC; -- Response Ready - zeigt an, ob der Master die Anwort empfangen kann (1 = ready)

-- Read Adress Channel Signale
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Leseadress-ID (immer 0; alle konfigurierten Kanäle haben Zugang zu einem einzelnen Adressbereich im Memory Map Interconnect...)
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- Leseadresse (erste Adresse Burstzyklus)
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); -- Burst Länge (exakte Anzahl von Transferen in einem Burst)
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- Burst Größe (Größe eines jeden Transfers im Burst; basierend auf Datenbreite des Interfaces)
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- Burst Type (gekoppelt mit Größeninformation, Details, wie jede Adressein einem Transfer zu adressieren ist,...)
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Lock Type; immer 0
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Cache Type; immer 0
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); -- Protection Type; immer 0
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Quality of Service; immer 0
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- Region Indentifier; immer 0
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); -- Read Adress Channel User; immer 0
m_axi_arvalid : OUT STD_LOGIC; -- Read Adress Valid; Angabe, ob gültige Read Adress- und Kontrollinformationen verfügbar sind (1 = valid)
m_axi_arready : IN STD_LOGIC; -- Read Adress Ready; zeigt an, ob der Slave bereit ist Adress- und zugehörige Kontrollinformation zu empfangen (1 = ready)

-- Read Data Channel Signale
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- Read ID Tag; ...; erzeugt im Slave; nicht genutzt im VFIFO
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Read Data
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- Read Response; zeigt den Status des Lesetransfers an (erlaubt sind: OKAY,EXOKAY,SLVERR,DECERR)
m_axi_rlast : IN STD_LOGIC; -- Read Last; letzter Transfer in einem Leseburst
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- wird im VFIFO nicht benutzt (wahrscheinlich einfach weitergeleitet?)
m_axi_rvalid : IN STD_LOGIC; -- Lesedaten verfügbar (1 = Daten verfügbar)
m_axi_rready : OUT STD_LOGIC; -- ob Master bereit ist die Lesedaten und Antwortinformationen zu bekommen (ready = 1)

------ Verbindung zu den Ein- und Ausgängen --------------------------
-- AXI4 Stream Slave (in)
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);   
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 

-- AXI4 Stream Master (out)
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);   
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);

------ Kontrollsignale -----------------------------------------------
vfifo_mm2s_channel_full : IN STD_LOGIC_VECTOR(1 DOWNTO 0);   -- channel full flag
vfifo_s2mm_channel_full : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- channel full flag
vfifo_mm2s_channel_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- channel empty flag
vfifo_idle : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
end component;



[Oleksandr Kiyenko]

Hello,

Parameters for MIG core is
MCB3, DDR3, MT41J64M16XX-187E,
Calibrated Input Termination - ZIO pin Y2, RZQ pin K7,
Single-ended System clock. Other settings is depend on your project.
You can use UCF for your chip from reference project - it contain calibration values.

As for ports count - it's depend on your project, think that 2 ports is minimal, additional ports can be used for data access and processing.

Best regards
Oleksandr

[Tobias Benkhoff]

Hello,

I have the same problem. I need to sample data and want to save these on DDR RAM before sending the data via USB to a computer.
Did you manage to communication between virtual fifo and RAM. Do you still know, how you have implemented the RAM?
Thanks
Best regards Tobias

[Oleksandr Kiyenko]

Hello,

We try Vivado Virtual FIFO Controller core and it's working as it should. But you should carry about:
1. Write block size
2. Virtual FIFO overflow (Can be hard to define)
3. Restrict access to memory area dedicated to virtual FIFO

Best regards
Oleksandr Kiyenko

[Oleksandr Kiyenko]

Sorry for previous post. There is no Virtual FIFO controller in XPS, only in Vivado. So for Spartan 6 you need to make you own
core. This core should write and read blocks to DDR RAM from/to some small buffering FIFO.
We don't have such core but there should be no problems to implement it as it have only standard interfaces and known logic.

Best regards
Oleksandr Kiyenko