Author Topic: Is fx2_core v1.50 fully functional?  (Read 4200 times)

westrice

  • Active Member
  • *
  • Posts: 13
Is fx2_core v1.50 fully functional?
« on: May 15, 2012, 12:03:03 AM »
Hi Forum,

Regarding the file fx2_engine.vhd from fx2_core v1.50, you can see in the top the following comment:

Code: [Select]
-- "r" test always failed
-- "w" test 20.8 MB/s

This means that only the TX is working on this version? (assuming that TX is the direction outwards from the FPGA)

Best Regards.
Westrice.

Oleksandr Kiyenko

  • Global Moderator
  • Sr. Member
  • *****
  • Posts: 397
Re: Is fx2_core v1.50 fully functional?
« Reply #1 on: May 15, 2012, 08:14:41 AM »
Hi westrice,
Try to do "r" test after "w". "w" test filling FPGA memory with data from PC and then check it. "r" test read memory and send it to PC. There is no memory filling at start, so if was no "w" tests, "r" test will fail because it send not initialized buffer to PC. It's was done because initial filling take several seconds and PC don't know when it finished.

Regards
Alex

Oleksandr Kiyenko

  • Global Moderator
  • Sr. Member
  • *****
  • Posts: 397
Re: Is fx2_core v1.50 fully functional?
« Reply #2 on: May 31, 2012, 02:51:51 PM »
Hi westrice,
Try new core xps_fx2 v1.50.b from https://github.com/Trenz-Electronic/TE-EDK-IP
Old one (1.50.a) have issue with Spartan-6 core generator which affect to transfer.

Regards
Alex

westrice

  • Active Member
  • *
  • Posts: 13
Re: Is fx2_core v1.50 fully functional?
« Reply #3 on: July 12, 2012, 08:00:30 PM »
Hi Alexander,

Still regarding the fx2_core v1.50b, where did you get the values for the timing constraints? (the OFFSET ones).

Best Regards.

Oleksandr Kiyenko

  • Global Moderator
  • Sr. Member
  • *****
  • Posts: 397
Re: Is fx2_core v1.50 fully functional?
« Reply #4 on: July 12, 2012, 08:14:11 PM »
Hi westrice,
This constrains mostly based on FX2 timing requirements, but this requirements is sometimes are impossible to implement in real project. With default synthesis and implementation settings flip-flops for input and output data and controls are placed into pads so we have minimal possible delay. I change some constrains to be equal this minimal delay, so if this constrains don't meed there is some issue with options.

Regards
Alex