Clock on TE0715-05-51I33-A

[Michael]

Dear,

We are working with an TE0715-05-51I33-A FPGA on the TE0705 carrier board. When running the example project, there seems to be no clock going to the PL. We measure

inputs:
fclk[0] : no clock
mgt_clk1 : clock signal (as expected)

PS outputs:
FCLK_CLK0 : no clock, constant high
FCLK_RESET0_N : low (active!)

We verified that the programming works and the measured pins are connected correctly by implementing some simple asynchronous logic.

We made no modifications to the TE0705 carrier board other than adjusting the output voltages to 3V3. According to our understanding of the documentation, this should work. We did not modify the example vivado project except adding output pins to measure the previously mentioned signals.

Does somebody have an idea what the problem could be? Is there some reset we don't see that stops the clock from being produced?

[MA]

Hi Michael,

we will answer you by email.

br