TE0808 PLL Lock Failure

[mer]

Hello, I'm using a TE0808 (TE0808-6BE21-A) on a custom carrier and I think I have everything working except for the reference clock for USB3. I have modified the TE0808/TEBF0808 FSBL to my needs and successfully checked the clocks from the SI clock chip. I am using Ref Clk 2 100Mhz for USB and Ref Clk 3 27Mhz for DisplayPort. It seems no matter what I get a GTR Lane 2 lock status failure (Reg:0xFD40A3E4). When I check PLL_REF_SEL2 (Reg 0x00FD410008) during FSBL execution I get 0xD which is 27Mhz.

PLL_REF_SEL0 (SERDES), Val:D)
PLL_REF_SEL1 (SERDES), Val:D)
PLL_REF_SEL2 (SERDES), Val:9)
PLL_REF_SEL3 (SERDES), Val:9)
Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz,
0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz,
0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135MHz,
0x11 - 150 MHz. 0x12 to 0x1F - Reserved

I tried to modify psu_init.c to force PLL_REF_SEL2 to 100Mhz and it seems to work (but lock still fails) in fsbl/uboot but after petalinux boots it reverts back to 27mhz.

FSBL:

PLL_REF_SEL0 (SERDES), Val:D)
PLL_REF_SEL1 (SERDES), Val:D)
PLL_REF_SEL2 (SERDES), Val:D)
PLL_REF_SEL3 (SERDES), Val:9)
Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz,
0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz,
0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz,
0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135MHz,
0x11 - 150 MHz. 0x12 to 0x1F - Reserved

Petalinux:

ZU6EG:~$ sudo devmem 0x00FD410000
0x0000000D
ZU6EG:~$ sudo devmem 0x00FD410004
0x0000000D
ZU6EG:~$ sudo devmem 0x00FD410008
0x00000009
ZU6EG:~$ sudo devmem 0x00FD41000c
0x00000009

I'm not sure what to check next! Thanks for any help.

[JH]

Hi,
DP will be setup with Linux....so it depends where you check the PLL status of the GTRs for DP.

We have some reference design online where we use USB and DP on TE0808 with TEBF0808. Prebuilt binaries are directly included, so you can test.
br
John