How to connect inout port

[bigguiness]

This is a stupid question but I can't find a solution anywhere....

I have a couple pins on my carrier board for a TE0720 that are bi-directional GPIOs. Currently I have an AXI GPIO in my block design and have the necessary pins defined as a port. The GPIO port is setup as bidirectional.

The problem is I can't figure out how to connect the 'gpio_io_i[4:0]', 'gpio_io_o[4:0]', and 'gpio_io_t[4:0]' lines from the AXI GPIO to the port 'IO[4:0]' that I defined.

What am I missing?

[Waldi3141]

Hi,

How and where did you define the GPIO port?

You could define a port in the board files like in the board xml file i attached(of the board files from TE0720_20_2I).
That way you can open a vivado project with appropriate board files and pull the port from the board tab into your block diagram.


 

[bigguiness]

I just checked an older project I had for an Arty Z7-10 board. On that board I have a similar ports defined as inout and they correctly get connected to a IOBUF primitive.

The only difference I found was in the "Generate Output Products" dialog.

For the Arty Z7-10 project, the Synthesis Options was set to "Global".

For the TE0720 project, it was set to "Out of context per IP". After changing it to "Global" the ports then got connected to IOBUF primitives.

So what's up with that option? Why does it default to "Generate Output Products" instead of "Global"?

Thanks

[JH]

Synthesise Block design IPs separately(no optimization between IPs but faster for development especially when you change parts only ) vs optimise all....see Xilinx documentation.
I could now imagine that you have a buffer in an IP, Vivado does not pass on the top (because not optimized beyond the limits) and there a second independently generated, then you have 2 connected in series which is usually physically not possible.

I would recommend to write buffer always on the top entity (in case of Block design, Vivado generates this normally automatically (if you select automatic generated top entity)). Use Xilinx floorplanner (IO planner view) to generate XDC file.

br
John

[bigguiness]

John,

Thanks for the reply.

But, most of that just buzzed over my head. I'm still pretty new at this FGPA stuff and am still learning how the Xilinx tools work.

Vivado I "kind" of get, other than still learning VHDL/Verilog. But there is a lot in it that I have not used, like the floorplanner.

Vitis isn't a problem, most of the time. It seems to just be a specialized IDE (Eclipse?).

The PetaLinux part always screws me up... That is going to be a problem later but right now I'm testing my hardware design in bare metal using Vitis.

Hartley

[JH]

Hi,

Vivado I "kind" of get, other than still learning VHDL/Verilog. But there is a lot in it that I have not used, like the floorplanner.

Run "RTL Analysis" to check how Vitis interpret your design (it generates some kind of general schematic)
Run "Synsthesis" --> Open Synthesized Design (translate it into device depended component). An in case View is not correct go to "Layout" --> IO Planning. You should see Zynq Package and I/O Ports. On this table you can select IO Pins and Standard and Vivado write xdc for you.
If this is OK run Implement (Here the design is mapped onto the FPGA, i.e. placed and connected.)

Note: PS on Vivado show only the configuration which is included into the xsa export for Vitis/Petalinux (so they know how the Zynq should be configured). PS Configuration is done only with FSBL not with bitstream!

But this are more Xilinx(AMD) specific questions, you should read Vivado Documentation  or ask on AMD(Xilinx ) forum

Vitis isn't a problem, most of the time. It seems to just be a specialized IDE (Eclipse?).

yes

The PetaLinux part always screws me up... That is going to be a problem later but right now I'm testing my hardware design in bare metal using Vitis.

there are many ways how you can bring up linux.

We have a reference design with petalinux template. Follow instructions and setup petalinux correctly (depends on the Vivado/Vitis/Petalinux version) and it should be possible to bring it up.
https://wiki.trenz-electronic.de/display/PD/PetaLinux
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board

br
John