Author Topic: questions on TE014s series - spartan 3  (Read 6216 times)

vibha_r

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questions on TE014s series - spartan 3
« on: November 22, 2011, 10:22:30 AM »
hallo,

I ama student working as an intern. I am dealing with a project regarding MJPEG decompression. I would like to know the following about the following eval board series (http://www.trenz-electronic.de/support/download-area/te0140-spartan-3-series.html ) :

1) Is Parallel port communication possible with this board? Because the input data is being received from a controller parallely.
2) Nothing is mentioned about the LVDS ports on this board. Is it available ? If not can this be made possible and how?
3) Can you provide a MJPEG decoding algorithm along with this board?

I request you to answer these questions to me as soon as possible.

Thanks and Regards,

Vibha Rao.

Thorsten Trenz

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Re: questions on TE014s series - spartan 3
« Reply #1 on: November 22, 2011, 10:49:59 AM »
Dear Vibha,

1) Is Parallel port communication possible with this board? Because the input data is being received from a controller parallely.

If you mean, you want to connect some IO's to a parallel data source, then yes. You need to take the IO Voltages into account. Spartan-3 is capable of 3.3V maximum. Also the VCCIO of the corrosponding IO's needs to be connected to the right source.

2) Nothing is mentioned about the LVDS ports on this board. Is it available ? If not can this be made possible and how?

IO's on this module are not routed differential. As the lines are short, it can work anyhow, but we do not support this.
If you need fully differential IO's, please use TE0300 or TE0600 instead.
http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/te0300-spartan-3e-series.html
http://www.trenz-electronic.de/products/fpga-boards/trenz-electronic/gigabee-xc6slx.html

3) Can you provide a MJPEG decoding algorithm along with this board?

No.

best regards
Thorsten Trenz

vibha_r

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Re: questions on TE014s series - spartan 3
« Reply #2 on: November 22, 2011, 11:09:37 AM »
1) Is Parallel port communication possible with this board? Because the input data is being received from a controller parallely.

By this i mean , I need to use parallel interface with an external microcontroller. How should I go about doing this?

2)  Nothing is mentioned about the LVDS ports on this board. Is it available ? If not can this be made possible and how?

If i use the TE300-sparan 3E series or the XC6SLX Series, is it possible to achieve the parallel interface with that?

3)Also an additional question:

Can I use extended memory (external memory) with all the 3 modules (TE014x, TE0300, XC6SLX Series) instead of the on board DDR SDRAM. Because I have heard it is easier to handle an external memory as it is less complex to program instead of the on board DDR SDRAM? Is his true? Because since I am dealing with video , I am assuming I will need more space than the block RAM.

 

Oleksandr Kiyenko

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Re: questions on TE014s series - spartan 3
« Reply #3 on: November 22, 2011, 01:05:11 PM »
Hello vibha_r.
As I understand you want to use some parallel bus interface with some external controller. You can use user I/Os wired to connector for this purposes.
But you need to write your own core to handle this bus interface. Also you need to take to account your external controller I/O voltage settings.
If you specify controller or bus interface type, it will be more clear to understand your needs.
Can I use extended memory (external memory) with all the 3 modules (TE014x, TE0300, XC6SLX Series) instead of the on board DDR SDRAM. Because I have heard it is easier to handle an external memory as it is less complex to program instead of the on board DDR SDRAM? Is his true? Because since I am dealing with video , I am assuming I will need more space than the block RAM.
As for using external memory, don't sure that it will be better solution. If you going to use SRAM as external memory (simplest interface) you will get much lower bandwidth and it considerably more expensive than DDR SDRAM. Others memory types even more expensive and have complex interfaces. Using Xilinx Core generator you can create memory interface core which will give you simplified memory access, writing own memory interface in most cases take long time, reqire debug and testing  and results will be worse. First of all you have to define reqired memory size and bandwidth, only after that you can choose module and other project options.
Regards,
Alex

vibha_r

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Re: questions on TE014s series - spartan 3
« Reply #4 on: November 22, 2011, 02:27:11 PM »
Hallo Alex and all others,

I am using the JCP2011 PL microcontroller which is connected to the FPGA via parallel interface. The JCP2011 PL is connected to an IP camera which is capturing the MJPEG video frames at a rate of 30frames/sec. (each frame is of VGA resolution i.e 640x 480 pixels). These frames are then transferred to the FPGA using DMA transfer. The transfer rate should be 30frames/sec to the FPGA. Once inside the FPGA, I assume there should be some buffering , for storing the frames. I think a size of 2 KB is sufficient . The frames are then sent for decoding , followed by buffering and serializing . The serialized frames are then sent back to the JCP for displaying via LVDS -out.

Thus I am unable to decide the actual memory size required .

How do I decide that? Because I think it should all depend on the way the decoding algorithm is working. Please guide me through , if you have any idea.

thanks and Regards,

Vibha

Antti Lukats

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Re: questions on TE014s series - spartan 3
« Reply #5 on: November 23, 2011, 11:34:48 AM »
any hint to the JCP2011 thing?
what type of interface it provides?

And what are you going todo inside FPGA?
2K byte of buffer seems very small?

Antti

vibha_r

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Re: questions on TE014s series - spartan 3
« Reply #6 on: November 23, 2011, 11:51:24 AM »
Hallo Antti,

The JCP2011 has no parallel interface, it has an expansion slot which must be configured for parallel interface.

the FPGA is supposed to perform decoding of video which is being received from the JCP at a rate of 30frames /sec. the decoded video is then serialized inside the FPGA and then is sent back to the JCP for display.

I am attaching a basic flow diagram for better understanding.

i am not able to decide what is missing in the diagram (FPGAblck.jpg)
how to decide the size of buffers?

regards
Vibha


Oleksandr Kiyenko

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Re: questions on TE014s series - spartan 3
« Reply #7 on: November 27, 2011, 05:35:13 PM »
Hello vibha_r!
Unfortunatelly I did't find information about your controller. You should check I/O voltage for parallel interface you going to use and write FPGA core to work with this interface.
As for memory requirements you should check requirements for blocks you going to use for example http://opencores.org/project,mjpeg-decoder to choose memory size and FPGA to fit your project.

Regards,
Alex