Petalinux FSBL & SI5338A

[koen_Schoutens]

Hello,

We are using the TE0715-04-15-2I with TEF1002 carrier.
I have downloaded the prebuild images. Using the prebuild Linux boots fine.

Using the sources I am able to build the Vivado and Petalinux project.
I have generated a patchfile for the Petalinux FSBL to generate the same FSBL as used in the Vitis software. Using the same source, the Vitis project is able to communicate with the onboard SI5338A.
When using the FSBL generated by Petalinux (using the patch file) the FSBL Hangs on the SI5338A init.

Code: [Select]

Xilinx First Stage Boot Loader
Release 2020.2  Sep  3 2021-12:38:34

--------------------------------------------------------------------------------
Xilinx First Stage Boot Loader (TE modified)
Release 2020.2  Sep  3 2021-12:38:34
Devcfg driver initialized
Silicon Version 3.1
WDT_RESET_OCCURED
Watchdog driver initialized
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60000000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 4
Partition Number: 1
Header Dump
Image Word Len: 0x00041CD0
Data Word Len: 0x00041CD0
Partition Word Len:0x00041CD0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000075D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFF3314E
Bitstream
In FsblHookBeforeBitstreamDload function
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x5802300F
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x50000F30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x00041CD0
PCAP DMA DEST LEN 0xF8007024: 0x00041CD0
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x0002CFE9
Data Word Len: 0x0002CFE9
Partition Word Len:0x0002CFE9
Load Addr: 0x04000000
Exec Addr: 0x04000000
Partition Start: 0x000492A0
Partition Attr: 0x00000013
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xF7F2FB30
Application
Partition Number: 3
Header Dump
Image Word Len: 0x00001378
Data Word Len: 0x00001378
Partition Word Len:0x00001378
Load Addr: 0x00100000
Exec Addr: 0x00000000
Partition Start: 0x00076290
Partition Attr: 0x00000013
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFE86083
Application
Handoff Address: 0x04000000
In FsblHookBeforeHandoff function
In FsblHookBeforeHandoff function

Device IDCODE: 373B093
Device Name: 7z015 (1B)
Device Revision: 0
--------------------------------------------------------------------------------
TE0715 TE_FsblHookBeforeHandoff_Custom
Configure TE715 SI5338
Si5338 Init Registers Write.

Is there a setting in Petalinux which I need? We are using the 2020.2 Xilinx toolkit.

[JH]

Hi,
can you enable debug flags of the FSBL and maybe add some more printf round si programming procedure. the question is if SI access fails or something after SI programming.

How did you create your patch? Did you use our 2020.2 fsbl or old one to generate the patch?

br
John

[koen_Schoutens]

Dear,
I have enabled the debug flags, as you can see.

After some debugging, we found the FSBL is stuck at

Code: [Select]

iic_write8( chip_addr, 246, 0x01); //Hard reset
This is verified using JTAG. This line returns '1' (fault). All the other I2C writes and reads also retun false.

I have attatched the patch file. We have used 2020.2 as the base.

[JH]

Hi,
I2C is enabled in your project? Does it work, when you generate FSBL with Vitis and your xsa?
I didn't notice anything in the patch file itself, maybe the compiler does something different with vitis than with petalinux.
br
John

[koen_Schoutens]

Exactly, using Vitis the FSBL is working (using the same xsa)
I2C is enabled. I am using the reference design of Trenz.

[JH]

Hi,
maybe Xilinx use different I2C drivers on petalinux generated fsbl and on vitis generated FSBL? You would now have to debug deeper and deeper where exactly it goes wrong when you use petalinux compiler.

Maybe it helps, when you ask additionally on Xilinx forum?
br
John