How to change pl clock speed?

[LQ1234]

Hello,

I am developing a design on the zynqberryzero (TE0727) based off of the reference design provided. I would like to change a clock speed in the programmable logic. In vivado, I configured the clock speed of a PL fabric clock in the Clock Configuration tab of the processing system ip. I then generated the bitstream and exported the hardware for vitis. In vitis, I updated the hardware specification and rebuilt the platform. Then I created and flashed an image with the built fsbl, the bitstream, and uboot. However, the clock speed remained the same as before:

Zynq> clk dump
clk      frequency
...
     fclk0            99999999
     fclk1           199999998
     fclk2            66666666
     fclk3            66666666


Sorry if this problem is simple; I am new to fpga design.

Thanks,
Larry

[JH]

Hi,
1 open Zynq IP in your vivado project and change PS-PL CLKs like you want
2 generate design and export new xsa file to Vitis
3. generate fsbl and application(optional, use for example hello world)
4. generate boot.bin
5. program QSPI Flash with new boot.bin
--> FSBL configure PS on power up

br
John