TEBF0808-04A Starter Kit configured for ADI FMCOMMS2 9361 Linux Boot Hang

[DenRyu]

Hello Trenz Forum,

I am looking for some design guidance and troubleshooting help on a design that uses a TEBF0808-04A Starter Kit with a TE 0803-01 Xilinx xczu3eg-sfvc784-1-e board that is going to communicate with an Analog Devices FMCOMMS2 AD9361 development board attached to the FMC connector. I have started with the ADI (Analog Devices Inc.) HDL project code and then integrated in the IP blocks and constraints for the TE Starter Kit in Vivido 2018.3 and was able to successfully build and export the hardware description file. Integrating in the Starter Kit device-tree and U-boot PetaLinux meta-user files I was able to successfully build the project using the ADI libraries/source (https://github.com/analogdevicesinc/meta-adi/tree/2019_R1/meta-adi-xilinx (Note: The master branch webpage has slightly better details) and https://wiki.analog.com/resources/tools-software/linux-drivers-all#building_the_adi_linux_kernel) but the system freezes during boot after the line "Starting kernel ..."

I have found recently that if I don't include the ADI libraries/source as User Layers (i.e. using PetaLinux default kernel) that the system does boot completely (but it is of course missing the necessary ADI drivers). I have successfully built using the same ADI libraries/source for custom hardware that has fewer and different devices than the Starter Kit but the same Xilinx part. Any insights on what could cause this hang during boot or ideas to try?

I am still very new to FGPA design so detailed explanations are greatly appreciated. Thank you.

[JH]

Hi,
can you show me the whole boot log one time, when it fails? Where did it stops?

br
John

[DenRyu]

It is configured to boot from the SD card. Here is the whole boot log:

Xilinx Zynq MP First Stage Boot Loader
Release 2018.3   Apr  7 2021  -  17:12:32
NOTICE:  ATF running on XCZU3EG/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 17:11:45, Apr  7 2021
PMUFW:  v1.1


U-Boot 2018.01 (Apr 07 2021 - 17:12:39 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  2 GiB
EL Level:       EL2
Chip ID:        zu3eg
MMC:   mmc@ff160000: 0 (eMMC), mmc@ff170000: 1 (SD)
Using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Board: Xilinx ZynqMP
Bootmode: SD_MODE1
U-BOOT for te_adi_dev

Hit any key to stop autoboot:  0
Device: mmc@ff160000
Manufacturer ID: 13
OEM: 14e
Name: Q2J54
Tran Speed: 200000000
Rd Block Len: 512
MMC version 5.0
High Capacity: Yes
Capacity: 3.6 GiB
Bus Width: 4-bit
Erase Group Size: 512 KiB
HC WP Group Size: 8 MiB
User Capacity: 3.6 GiB WRREL
Boot Capacity: 16 MiB ENH
RPMB Capacity: 512 KiB ENH
reading image.ub
21627508 bytes read in 1414 ms (14.6 MiB/s)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  gzip compressed
     Data Start:   0x10000100
     Data Size:    7600748 Bytes = 7.2 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x00080000
     Entry Point:  0x00080000
     Hash algo:    sha1
     Hash value:   b0a95e6f506ef537be2fd0608581b8258b5517e8
   Verifying Hash Integrity ... sha1+ OK
## Loading ramdisk from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'ramdisk@1' ramdisk subimage
     Description:  petalinux-user-image
     Type:         RAMDisk Image
     Compression:  gzip compressed
     Data Start:   0x1074998c
     Data Size:    13984597 Bytes = 13.3 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: unavailable
     Entry Point:  unavailable
     Hash algo:    sha1
     Hash value:   b682c715bb91600c7e7d2ddc7e3b7beb3a5641f4
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x1073fc70
     Data Size:    40024 Bytes = 39.1 KiB
     Architecture: AArch64
     Hash algo:    sha1
     Hash value:   eb92f58998a6e185d821a15f8dbfaddb7e59e2fb
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x1073fc70
   Uncompressing Kernel Image ... OK
   Loading Ramdisk to 072a9000, end 07fff355 ... OK
   Loading Device Tree to 000000000729c000, end 00000000072a8c57 ... OK

Starting kernel ...

[JH]

Hi,
can it be that you has assigned print to another uart port for linux?

UART port can be different for FSBL, UBOOT and Linux.  If logs end on this stage, it's mostly  this problem that other port for outputs is used.

br
John

[DenRyu]

Hi John,

If it is, I don't know where that configuration lives. I've verified in petalinux-config, "Subsystem AUTO Hardware Settings->Serial Settings-> Primary stdin/stdout (psi_uart_0)" and in the same submenu "System stdin/stdout baudrate (115200)" as I would expect. The Zynq UltraScale+ IP Block in Vivado is configured to use "MIO 42 .. 43" for UART 0 and UART 1 is unchecked/unused.  I have attached my built device tree source (.dts file converted using the Linux dtc tool) in hopes that might help unveil something. Is there another place that the UART could be affected or configured?

I reverified today that I can still boot successfully using the 2018.3 Starter Kit prebuilt images just fine and output from "lspci" and lsusb" look good to me. Also, it may be notable that the ADI Linux version is 4.14.

Thanks again for your assistance!

[JH]

Hi,
uart looks OK on device tree, but as I know there are also some other linux options possible to forward uart prints to other port.

Can you try following.

Use our 2018.2 template project and your xsa file and generate linux files without any changed and check if it works.
If it works, start to add ADI drivers and regenerate linux.

Second option to check if linux is available is to add fix IP to you linux system and use for example putty to connect to the the system via SSH.

br
John

[DenRyu]

I configured a static IP in petalinux and I was unable to connect or ping the TEBF0808 so it still seems that it is freezing while booting. I verified that my method worked with a different working build first and was able to ping and ssh successfully with that setup.

I also used a built the 2018.3 Starter Kit project and then added my XSA configuration file and was able to build and boot the TEBF0808 system using both default petalinux linux/kernel and the ADI linux/kernel. The build however doesn't include the ADI IP blocks and configuration Vivado which are necessary to support the ADI FMCOMMS2 FMC dev card.  Starting with the Starter Kit Vivado project and integrating in the ADI hdl appeared to be a more difficult and risky path than integrating the Starter Kit in to the built ADI FMCOMMS2 project. What I essentially did for that was to add the provided Starter Kit IP folders to the project, edit the zusys_bd.tcl file (attached) slightly so it didn't make any of the connections to the Zync+ and then copy what that generated in to my design and make the remaining adjustments and connections to the Zynq+ in my design. Perhaps something in that process is causing this issue?

Does there happen to be a guide that explains how to integrate the Starter Kit IP in to a user/custom project?

Thank You

[JH]

Hi,
you mean the "SC0808BF" IP , "rgpio" IP and "axis_live_audio_1.0" IP.
--> open IP catalog --> right click on the catalog and add local repo --> set path to \StarterKit\ip_lib of the reference design

But this 3 IPs are optional. It's only to show how you can get acces to CPLD and map some IOs for Audio CAN, LED and CPLD

I would suggest following:
Create Starterkit design completely by yourself without any changes, mean Vivado Project, XSA export FSBL(with our template), petalinux...final boot.bin and image.ub (I think you has done this or?)
If this works add your ADI PL IPs to this Vivado Project and also change PS settings if necessary.  --> regenerate all files again without any additional  change (means  XSA export FSBL(with our template), petalinux...final boot.bin ) and check if this still boots.
If this works start to modify petalinux for ADI

br
John

[DenRyu]

Hi John,

I've finally figured out the root cause of this issue. It ended up being as simple as needing to include the exported bitstream in the petalinux-package command using the --fpga option to point to the file. I didn't realize it was necessary for this design but I had been doing that previously for the other hardware platform I originally mentioned due to adding a couple GPIO signals. I've gained some more experience the hard way it seems. Thank you for your helpful replies though as it aided me to rule out a few things so I didn't spend additional time debugging.

[JH]

Glad to hear that it works now.
br
John