Install Problem

[Volker]

Hi,

I am trying to create a sample project. I have installed Ubuntu 20.04 LTS and Vivado 2020.2.
I am running the _create_linux_setup.sh

- 0 Module selection guide
- 6 TE0720-03-1CFA
- 1 Create Vivado project

Vivado starts up and this is the output of the tcl console with an error:

Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/volker/test_board/constraints/_i_common.xdc
 /home/volker/test_board/constraints/vivado_target.xdc
 /home/volker/test_board/constraints/_i_TE0720-SC.xdc
 /home/volker/test_board/constraints/_i_bitgen_common.xdc
  ------
Set processing order normal for /home/volker/test_board/constraints/_i_common.xdc
Set use for implementation only for /home/volker/test_board/constraints/_i_common.xdc
Set processing order normal for /home/volker/test_board/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/volker/test_board/constraints/vivado_target.xdc
Set processing order normal for /home/volker/test_board/constraints/_i_TE0720-SC.xdc
Set use for implementation only for /home/volker/test_board/constraints/_i_TE0720-SC.xdc
Set processing order normal for /home/volker/test_board/constraints/_i_bitgen_common.xdc
Set use for implementation only for /home/volker/test_board/constraints/_i_bitgen_common.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/volker/test_board/block_design/zsys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zsys_bd
  TE::PR_TOPLEVELNAME: zsys_wrapper
  ------
  TE::IS_ZSYS:         true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/volker/test_board/block_design/zsys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0720_1q:part0:1.0, FPGA: xa7z020clg484-1q at 2021-01-08T07:45:53.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD::TCL 103-2003] Currently there is no design <zsys> in project, so creating one...
Wrote  : </home/volker/test_board/vivado/test_board.srcs/sources_1/bd/zsys/zsys.bd>
INFO: [BD::TCL 103-2004] Making design <zsys> as current_bd_design.
INFO: [BD::TCL 103-2005] Currently the variable <design_name> is equal to "zsys".
INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog: 
trenz.biz:user:SC0720:* xilinx.com:ip:processing_system7:* xilinx.com:ip:vio:* xilinx.com:ip:xlconcat:*  .
WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins processing_system7_0/IIC_1'
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: .
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: .
ERROR:(TE) Script (TE::INIT::run_board_selection) failed: .
ERROR:(TE) Script (TE::main) failed: .
update_compile_order -fileset sources_1


I am out of ideas. Can anybody help please ?

Volker

[JH]

Hi,
can you send me the whole log file.  it's in the subfolder v_log. Can you also send me the zip name and your exact vivado release number(see Vivado "Help --> about Vivado")

br
John

[Volker]

Hi John,

Vivado v2020.2 (64-bit)
SW Build: 3064766 on Wed Nov 18 09:12:47
IP Build: 3064653 on Wed Nov 18 14:17:31

Log File is attached.

Thanks

Volker

[JH]

Hi,
on my place it works fine. Different between your and my project starting is that you use the Xilinx Board Store installation (which is betaversion for my scripts at the moment).

Maybe something goes wrong with board store installation or you has some older board files installed (2020 Boad Files was updated at theduring feburary this year on Xilinx board store, maybe your vivado version has installed some older one?).
Can you delete your whole TE0720 project, unzip  the download again again and run again(TE0720-test_board-vivado_2020.2-build_2_20210217064913) and project creation. But this time without board store, use default local board file installation.

Note: Can it be that you also installed Vivado only? For SoC devices you need also Vitis (Vitis installation contains also Vivado).

br
John

[Volker]

Hi John,

deleting and reinstalling leads to the same problem.

I did not work with vitis before. Last Vivado I was working with was 2018.
I have installed Vivado Webpack, wich is to my opinion the same as the
vitis download ( same MD5 ).

I will download this again and see if I did something wrong while installing...


Volker

[JH]

Hi,
hm strange. I've test also board store files and project also works on my place, see screenshot on the attachment.

So please let me know if local version works.

PS: Yes you are write installer is the same but you can select if you want to install Vitis (with Vivado) or Vivado only and since 2020.x also petalinux.
You has both a Zynq Module. for Zynq you must also generate FSBL to initialise PS part of the System. Vivado project includes the PS setup in the IP, but bitstream did not initialise PS. This will be done by FSBL.

br
John