TE0745 boot from QSPI

[aramsam]

Hi,

I have a TE0745 module and also the TEB0745 baseboard to evaluate it. I have done a PL design in vivado and a test application in Vitis that reads and writes some registers via an axi peripheral. The whole application is working if I program via JTAG in vitis.

Now I am trying to program the whole package in the QSPI flash on board the module and I cant seem to get the PL configured.

When I create a bootimage from vitis, my bif file looks like this :

Code: [Select]

the_ROM_image:
{
 [bootloader] D:/zynq/te045_psc/test_board/workspace/sdk/TE0745-02-71I11-A/export/TE0745-02-71I11-A/sw/TE0745-02-71I11-A/boot/fsbl.elf
 D:/zynq/te045_psc/test_board/workspace/sdk/axitest/_ide/bitstream/test_board_30_1i_1gb.bit
 D:/zynq/te045_psc/test_board/workspace/sdk/axitest/Release/axitest.elf
}

I select program flash in vitis and choose the generated bin file from above step. The flashing is successful and when I power cycle the board, I can see the baremetal application starting and hanging in the step where it tries to access the fpga registers. This usually happens when the fpga is not configured.

I added some constraints for the PL pins that i use in my application, but otherwise its default what the reference design provides. _i_bitgen_common.xdc has :

Code: [Select]

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

I am new to this Zynq SoC and would be thankful for any pointers.

Thanks in advance.

Ram

[JH]

Hi,

I select program flash in vitis and choose the generated bin file from above step. The flashing is successful and when I power cycle the board, I can see the baremetal application starting and hanging in the step where it tries to access the fpga registers. This usually happens when the fpga is not configured.

this can also happens if your PL IP axi addresses are wrong  and PS get never answer or or you has timing issues and ip does not work like expected.

There is a done LED on the module which indicates that the design is not programmed (LED is on in this case):
https://wiki.trenz-electronic.de/display/PD/TE0745+TRM#TE0745TRM-LEDs

Note: done Pin can be controlled by user design (you must active add  IP for access), as long as you didn't do this, you see  if PL part is programmed or not.

PS: we offer also some reference designs:
https://wiki.trenz-electronic.de/display/PD/TE0745+Reference+Designs

br
John

[aramsam]

Hi John,

Thanks for the quick reply.

The full design is working via JTAG. I can access registers and read & write. No hanging , all good.

The Red LED is not on. I have also not used it in my design. So this indicates that the PL is not configured.

In searching the forum here, i saw some of the other modules have some constraints regarding qspi. is this also needed here so that FPGA is configured during boot ?

I based my design also completely from your reference design for 2019.2. I used the supplied tcl scripts for everything.

Thanks for your support.

Ram

[JH]

Hi,

The Red LED is not on. I have also not used it in my design. So this indicates that the PL is not configured.

https://wiki.trenz-electronic.de/display/PD/TE0745+TRM#TE0745TRM-LEDs
-->    Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured.
This indicates PL  is programmed.

Open Vivado HW Manager and connect JTAG and check status there

Your bitstream is the correct one? Maybe Vitis use some older version sometimes there are a lot of copies, maybe some update was wrong

br
John

[aramsam]

Hi John,

Thanks very much. you are absolutely right. The bit file was wrong. I assumed that while exporting from vivado, clicking "include bit stream" will automatically includ the right one. But, this is not the case.

Now I am able to flash and see that after boot both PS & PL are loaded and working perfectly.

Thanks again for the speedy support.

Ram