Author Topic: Si5338 clock generation and FSBL  (Read 150 times)

Sheshu

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Si5338 clock generation and FSBL
« on: January 08, 2021, 11:50:10 AM »
Hello,

I'm regenerating FSBL for a  Block design with Ultrascale+ for the TE SoM board TE0820 (zu4cg).
I'm trying to use the SI5338 clock (200MHz) to trigger some ILA cores in my design.
After programming the new FSBL (generated according to the info (https://wiki.trenz-electronic.de/display/PD/PetaLinux+TE-Template#PetaLinuxTETemplate-PetaLinux2019.2), I see that the ILAs are not getting the free running 200MHz clock. According to the messages from Hardware manager I get these messages:
---
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
---
My queries are:
1. Is there some default ROM configuration available for Si533B already for 200MHz clock generation ?
2. How do I program the Si533B during power up before u-boot execution ?
3. Is there some reference code available how I can program the clock generator during the fsbl configuration ?

Hoping to get a reply asap.

Regards
Sheshu

JH

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Re: Si5338 clock generation and FSBL
« Reply #1 on: January 08, 2021, 01:28:17 PM »
Hello,
SI5338 is default not programmed.
this will be done via FSBL. Our reference design includes FSBL source code with our modification. See also reference design description in our wiki for TE0820.
br
John