FSBL for TE0820

[jhane]

Hello,
   I have a question about the FSBL's in the release.  I understand that one is special version for flashing an empty flash.   However, what is the second one for?  I see it has support for i2c and the clock chip.    Is this just so ethernet will work?   We do not have ethernet on our custom carrier and the FSBL generated from the xsa seems to work fine.
   Is there anything in the modified FSBL that I should be patching my generated FSBL with?

thanks,
jeff

[JH]

Hi,
ETH and OTG reset are also included:
https://wiki.trenz-electronic.de/display/PD/TE0820+Test+Board#TE0820TestBoard-zynqmp_fsbl.1


PS: You can load our template into Vitis as local repository (use  the same Vitis version otherwise Xilinx changes are not included). All our Changes are in separate files.
Load repo, see: https://wiki.trenz-electronic.de/display/PD/Vitis#Vitis-Includelocalrepositories

br
John

[jhane]

Thanks JH,
  I knew about the ethernet but not the OTG.  However, we only support host so don't need that either.  This is probably why the generated FSBL is working find for us.

jeff

[JH]

Hi,
sorry OTG means the USB PHY. It's the same PHY for host an OTG usage. It should be work also without usb phy reset for newer vivado version (Xilinx has integrated USB reset into PS IP, so I think drivers will also reset usb phy).

br
John

[jhane]

That's interesting.  We are using 2020.1.  I have a USB-C ethernet adaptor plugged and sometimes the devices is not recognized.   This makes me wonder if there is an issue with this reset.  I'll have to investigate this further.

thanks,
jeff