TE0720 No ethernet connection (CLK=0Hz)

[ahenric]

Hi,

we use the TE0720 board successfully so far, but since a design change (adding new encoder in Vivado) and rebuilding petalinux image, our Ethernet doesn't work anymore. We see the following:

Configuring network interfaces... udhcpc (v1.22.1) started

Sending discover...

Sending discover...

xemacps e000b000.ethernet: Set clk to 0 Hz
xemacps e000b000.ethernet: link up (100/FULL)
Sending discover...


Normally, when everything is working, it looks like this:

Configuring network interfaces... udhcpc (v1.22.1) started

Sending discover...

Sending discover...

xemacps e000b000.ethernet: Set clk to 25000000 Hz
xemacps e000b000.ethernet: link up (100/FULL)
Sending discover...



What could be the reason for this? We haven't changed anything on the Ethernet side. Attached please find our configuration and terminal output for the project which works and the one which doesn't.

[JH]

Hi,
which carrier did you use?
Can you try out our reference design please?
https://wiki.trenz-electronic.de/display/PD/TE0720+Test+Board
--> prebuilt Boot.bin and image.ub to boot from SD are included.


Ok can it be you try out an external PHY over MII to RGMII (like on TE0706 carrier)?
In this case you can normally ignore this message with 0Hz. Xilinx has often problems with 2 or more ETH. Depending on connection and Vivado/petalinux version, there are sometime patches need or changes in device tree or .... and sometimes there apears messages which are not correct.

For TE0706 we have only an older design. I've start tu update to 19.2 but it doesn't work at the moment. I didn't found a solution at the moment. So I can only refer to the old project:
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0720/Reference_Design/2016.2/carrier_te0706_eth

br
John

[ahenric]

We have used our own carrier, but the ethernet connector is directly connected to the TE0720. And as I have mentioned, the same carrier board and TE0720 works with a different FPGA bit file. So if you look at the files I have attached, one version works and displays the clock correctly, the other one not.

So what are possible configurations to look at that could cause this?

[JH]

Hi,
sorry compare your files is not part of our free service.

Did you use different Vivado/Petalinux version?


It can also be a problem of your vivado project (not included), generated fsbl....maybe one project was corrupted....

br
John

[ahenric]

Hi,

we use the same Vivado and Petalinux versions for all projects.

[JH]

Did you use different PS setup in your Vivado project? Maybe one is also enabled ETH0 to on board ETH PHY and ETH1 to your external PHY? And the second one not?
br
John