SEM-IP freezes in State transition after initialization

[Sid1511]

SEM-IP does not change state(freezes) after INIT OK message

Hi,

I am using a Zynq Ultrascale+ MPSoC (xczu9eg-ffvc900-1-e) with evaluation kit from Trenz electronics. I am trying to implement configuration scrubbing and error injection using ultrascale architecture SEM-IP. I used the following video as a tutorial to do it: https://www.youtube.com/watch?v=Rja88BR9IxA

The block diagram and the code in the PS (A53) is very similar to the one in the video tutorial.
When I execute the program, the initialization message shows up in the SDK terminal which states everything is OK and then it freezes without changing the state, as shown in the figure attached with this post along with block diagram and code:

It stops at SC instead of printing SC 02

I have switched the control from PCAP to ICAP as well and the clock given to SEM-IP and SEM UART is 100MHZ.

I do not have an idea of what is causing this issue. Looks like the ICAP has control and initialization is done properly. I did not notice any such cases in the SEM-IP related forums

please help me with this issue.

Thank you

[JH]

Hi,
You mean TE0808 TE0808-04-9BE21-A or TE0808-04-9BE21-L  --> MPSoC (xczu9eg-ffvc900-1-e)  is not always unique...we offer mostly different assembly versions (also other  flash size, DDR size.... ).
Which carrier did you use? TEBF0808?

I never worked with this IP....so I can't give you directly a good hint.

At first you should check timing constrains. They are OK? Are there additional constrains which must be set manually by user (see documentation of this Xilinx IP). Do you have unconstrained path which can be relevant?

--> https://www.xilinx.com/products/intellectual-property/sem.html#documentation

it looks like there are additional timing and placement constrains needed:
--> https://www.xilinx.com/support/documentation/ip_documentation/sem_ultra/v3_1/pg187-ultrascale-sem.pdf

To make it easier, do following: Right Click on the IP and export example designs. -->Check the assemble design constrains and connections. --> But it depends a little bi on the example if this helps

You can also add VIO or ILA debug core to monitor some of the signal.

PS: Maybe you should also write into Xilinx forum, this looks more like SoC internal stuff, so there is a bigger community which can help on this topic

br
John

[Sid1511]

Hi John,

Thank for your reply.
Its TE0808-04 DDR4 2GB RAM one. Along with TEBF0808 base board.

I have posted my problem in Xilinx Forum as well. The timing constraints are fine.
I managed to find out the problem. Its with my C code for UART. For some reason the interrupts do not recognize the last few bytes of data from SEM-IP.

Thank you

Regards

Siddarth