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Trouble generating custom SDSoC platform for TE0802

Started by jonbho, March 02, 2020, 07:24:46 PM

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We are trying to prepare the SDSoC platform for the TE0802 development board using Petalinux, in order to synthesize and run our HLS technology on the ZU2CG (we have been testing with the Zynqberry before). We can't use the supplied Petalinux and hardware platform since we need to have a different hardware IP schematic with proc_sys_reset_* signals, clocking wizard, etc... instead of the supplied hardware design with the VGA controller, 7-segment display, etc.

To help with this, we have been using the following guides:

We are able to prepare our own hardware design on Vivado and export our own DSA from the HDF using Vivado. Then, using the base template from TE0802 reference design, we can compile our own Petalinux with our own configuration. Finally, from SDSoC, we import our own generate DSA, and when we progress to the step "Add Processor Group/Domain", we reach the following error: "The given processor instance psu_cortexa53_2 does not exist in the hardware design ". Here is a snippet from the log file, showing the full context:

TRACE::2020-02-28.17:46:22::SCWWriter::formatted JSON is {
"platformName": "te0802_platform",
"sprVersion": "1.1",
"mode": "gui",
"dsaType": "Expandable",
"platformDesc": "te0802_platform",
"platHandOff": "D:/Xilinx/vivado_workspace/TE0802/te0802_board.dsa",
"deviceType": "zynqMP",
"platIsPrebuiltAutogen": "false",
"platPreBuiltFlag": false,
"platformSamplesDir": "",
"platActiveSys": "sysconfig1",
"systems": [{
"systemName": "sysconfig1",
"systemDesc": "sysconfig1",
"sysIsBootAutoGen": "false",
"systemDispName": "sysconfig1",
"sysBootDir": "D:/Xilinx/vivado_workspace/TE0802/BOOT",
"bootBifFile": "D:/Xilinx/vivado_workspace/TE0802/BOOT/boot.bif"
ERROR::2020-02-28.17:46:37::SCWSystem::The given processor instance psu_cortexa53_2 does not exist in the hardware design
LOG::2020-02-28.17:46:37::SCWSystem::Valid processor instances are psu_cortexa53_0 psu_cortexa53_1 psu_cortexr5_0 psu_cortexr5_1 psu_pmu_0

We have been investigating why SDSoC may be trying to use the 3rd core (which is of course missing in the ZU2CG, which only has two cores). We thought it may be due to U-Boot, since internally it is selecting a 4-core configuration (CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="xilinx_zynqmp_zcu102_rev1_0_defconfig"), but even if we disable U-Boot from the configuration (commenting out the #CONFIG_SUBSYSTEM_UBOOT_CONFIG_PETALINUX=y section), it still shows the error.

Any idea what we are doing wrong and how we can generate the SDSoC platform support files?

(We are using Vivado/SDK/SDSoC 2018.3.)


  -- Jon


sorry I don't know why this happens. It seems that SDSoC think you should have up to 4 CPUs, but your CG has only 2.

I found the same issue only on vitis:
--> on vitis this happens when you update the platform from a CG variant again. Generation project from scratch works, maybe you has the same problem.

We have use SDSoC the last time with 18.2 on TE0803 also with CG variant:
--> maybe you can try out to generate this project and than check the differences (It works with 2018.2 only).

But in general, you should start with 19.2 and Vitis, because Xilinx stopped SDSoC and works now with new Vitis intigration (they changed a lot of things):



Thank you John. We went with 2018.3 because the online resources provided by Trenz seem to provide support for that version:

Is there any documented way to adapt these to Vitis? We are happy to move one, we have been using Vitis with Alveo cards and we love it.


  -- Jon


generate the project with 18.3, close and open again with Vivado 19.2 --> Update IPs and generate XSA (it's like hdf) for Vitis and Petalinux.
If this update works out of the box depends on Xilinx IP changes, but you should try out.

We will update our reference designs also, but we  have a lot if different modules and boards, so it will take some time.