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TE0820 clock

Started by Dehim, February 26, 2020, 03:20:32 PM

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Dehim

February 26, 2020, 03:20:32 PM
Hello everyone,

I'm currently working with the TE0820-03-2AE21FA module.
This module has 3 on board clocks:

  • CLK0_P/N @ J9 and K9
  • B505_CLK1_P/N @ E21 and E22
  • B505_CLK3_P/N @ A21 and A22
At first I wanted to use the CLK0 input, since the other two clock inputs are PS-GTR reference clocks and CLK0 is connected to an HP I/O bank. This wouldn't work however, since for some reason CLK0 is not connected to a Global Clock capable I/O pin.

Then I tried to use CLK1 as the clock input. The TRM said this input could be used as a clock input, by instantiating a IBUFDSGTE buffer in the design.

So I did this, but the design failed with error
Quote[Place 30-68] Instance IBUFDS_GTE4_inst (IBUFDS_GTE4) is not placed
as well as critical warning
Quote[Vivado 12-1411] Cannot set LOC property of ports, Site PS8_X0Y0 is not part of a diff pair

From this thread I gathered that the ODIV2 output of IBUFDS_GTE4 must be used and connected through a BUFG_GT. So I did this and got the same critical warning and this error:
Quote[Place 30-640] Place Check : This design requires more BUFG_GT cells than are available in the target device. This design requires 1 of such cell types but no compatible site is available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.

Im using Vivado 2017.2 and used to following constraints to define the gtr clock input:
Quoteset_property PACKAGE_PIN E21 [get_ports gtr_clk_1_p]
set_property PACKAGE_PIN E22 [get_ports gtr_clk_1_n]

Is it even possible to use the PS-GTR reference clocks as PL clocks in a zu2cg-sfvc784?
Why isn't CLK0 provided to a GCIO pin? This part really bothers me. If instead I define the clock pins to be GCIO pins, implementation and bitstream generation proceed just fine.

Thanks in advance.

-Dehim

JH

#1
February 26, 2020, 04:05:50 PM
Hi,
GTR is PS (Processing part) and not PL(Processing logic--> FPGA part)

What you try to do works only for PL MGTs, which are not available on TE0820 module.

For GTR see:
https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf

br
John

Dehim

#2
February 26, 2020, 04:15:44 PM
Thanks for your reply JH,

That's what I figured, but the TRM clearly states:
QuoteA 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Why isn't the CLK0 signal connected to a GCIO pin? Perhaps this issue can be resolved in a later revision of the board? I can get my design to work by instantiating the processing system and using its clock output, but I don't want to use the Zynq PS just to get a clock signal.

JH

#3
February 26, 2020, 04:28:05 PM
It seems that is a stupid copy passed mistake.
it's not possible.
I will remove this wrong note from the trm.
br
John

Dehim

#5
February 26, 2020, 04:41:41 PM
Hi John,

Thanks for fixing that issue in the TRM.

I have looked at that test-board, but it doesn't actually use the si5338_clk0 input as a clock source. It uses the pl_clk0 as the clock source and only measures the frequency of the si5338_clk0 input.

JH

#6
February 27, 2020, 08:07:25 AM
???
instead of measurement you can also use this si5338_clk0 for other purpose....

br
John

Dehim

#7
February 27, 2020, 09:56:45 AM
Alright, so if I instantiate an IBUFDS in VHDL I get the following error:
Quote[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
   < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IBUFDS_inst/O] >

   IBUFDS_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X2Y99
    s_se_clk_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y47

   The above error could possibly be related to other connected instances. Following is a list of
   all the related clock rules and their respective instances.

   Clock Rule: rule_bufgce_bufg_conflict
   Status: PASS
   Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
   used at the same time
    and s_se_clk_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y47

Which I don't get if I locate the clock input to for instance K4 and K3, which is a GCIO capable site. K9 and J9 is not a GCIO capable site. The question still stands, why isn't the clock input connected to a GCIO capable site?

If I instantiate the utility buffer in a block diagram, Implementation proceeds without an error, but I do get the following warning:
Quote[DRC CKLD-2] Clock Net has IO Driver, not a Clock Buf, and/or non-Clock loads: Clock net IBUFDS_inst/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O is directly driven by an IO rather than a Clock Buffer or may be an IO driving a mix of Clock Buffer and non-Clock loads. This connectivity should be reviewed and corrected as appropriate. Driver(s): IBUFDS_inst/util_ds_buf_0/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/IBUFCTRL_INST/O

Furthermore, this solution feels like a bodge, since the only reason I would need a block diagram would be to route the clock. Adding the constraint they mention in the previous error also feels like a bodge, since this wouldn't be necessary if a GCIO pin was used. Furthermore, adding this constraint would mess up the placement of the MMCM I use, which would require an additional constraint to fix it in place.

JH

#8
February 27, 2020, 10:29:44 AM
It doesn't mean that you can't use them.

See: https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf


CG Pins are available over B2B connector. there was non left, which we can use internal for the PLL CLK, so we connect the PLL CLK to normal Pin (it's better than not connected)
For possible CG pins, see schematics.
https://shop.trenz-electronic.de/de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0820/REV03/Documents
we add notes to page 2 (B2B-Connectors)

In the most cases customer create own carrier, so customer can decide what should be connected on these pins

The most of our evaluation carrier have these pins available on the carrier connector.

On Module itself, you can use:
PS-PL CLKs (mostly recommended, but not in case you need low jitter clk)
This one PL CLK, so in this case add "< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IBUFDS_inst/O] >" constrain

In case you has special requirements on the CLK, you must connect external clk.

br
John

Dehim

#9
February 27, 2020, 11:19:25 AM
Ok, so I'll use that constraint for now.

Do you offer a carrier board that does provide a clock input to a GCIO pin of the TE0820 module? I've looked around on your website, but I couldn't find any.
I'm currently using a TE0703-04 board, which doesn't offer a clock to a GCIO pin. Perhaps it's an idea to offer a carrier that provides this capability?
This would ease development for projects that use your modules.

-Dehim

JH

#10
February 27, 2020, 11:22:48 AM Last Edit: February 27, 2020, 11:30:52 AM by JH

Dehim

#11
February 27, 2020, 12:36:00 PM
Hi John,

Thanks for your replies.
I get that I could use an external clock. It's just that it would be very nice if there was a carrier board with an on board clock that I could use.

-Dehim

ITS

#12
August 17, 2023, 01:44:44 PM
I just wanted to let you know, I had run into exactly the same problem.
Will probably use CLOCK_DEDICATED_ROUTE FALSE on that pin.
My goal is low jitter over several ms, I do not need to constrain the exact delay because all clocks are routed via FPGA (output).
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