Author Topic: TE0820 - 2019.2 Reference design - create_project failed  (Read 712 times)

luca_osrf

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TE0820 - 2019.2 Reference design - create_project failed
« on: February 11, 2020, 08:26:35 AM »
Hi all,

I'm trying to migrate our designs from the 2019.1 to the 2019.2 (and Vitis) tools.
As a first step I downloaded the reference design for the TE0820 module from the download area and am trying to create a basic project just to get a feeling of the tools.
We have a TE0820 with the 03EG fpga module so I set the board ID to 22, and it seems to be correctly found (I can see the details), however the script still returns an error saying that it was not found and the project is not created.
I tried both setting it in the design_basic_settings.sh file or doing so in the menu, both didn't end successfully.
The output, without module selection, is the following:

Code: [Select]
luca@luca:~/Downloads/test_board$ sh vivado_create_project_guimode.sh
------------------------Set design paths----------------------------
-- Run Design with: vivado_create_project_guimode.sh
-- Use Design Path: /home/luca/Downloads/test_board
---------------------Load basic design settings---------------------
--------------------------------------------------------------------
------------------Set Xilinx environment variables------------------
-- Use Xilinx Version: 2019.2 --
--Info: Configure Xilinx Vivado Settings --
--Info: Configure Xilinx SDK Settings --
--Info: Configure Xilinx LAbTools Settings --
-- Info: /opt/Xilinx/Vivado_Lab/2019.2/.settings64.sh not found --
--------------------------------------------------------------------
----------------------check old project exists--------------------------
Found old vivado project: Create project will delete old project!
Are you sure to continue? (y/N):
y
----------------------Change to log folder--------------------------
/home/luca/Downloads/test_board/v_log
--------------------------------------------------------------------
-------------------------Start VIVADO scripts -----------------------

****** Vivado v2019.2 (64-bit)
  **** SW Build 2700185 on Thu Oct 24 18:45:48 MDT 2019
  **** IP Build 2699827 on Thu Oct 24 21:16:38 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           test_board
  TE::VPROJ_PATH:           /home/luca/Downloads/test_board/vivado
  TE::VLABPROJ_PATH:        /home/luca/Downloads/test_board/vivado_lab
  TE::BOARDDEF_PATH:        /home/luca/Downloads/test_board/board_files
  TE::FIRMWARE_PATH:        /home/luca/Downloads/test_board/firmware
  TE::IP_PATH:              /home/luca/Downloads/test_board/ip_lib
  TE::BD_PATH:              /home/luca/Downloads/test_board/block_design
  TE::XDC_PATH:             /home/luca/Downloads/test_board/constraints
  TE::HDL_PATH:             /home/luca/Downloads/test_board/hdl
  TE::SET_PATH:             /home/luca/Downloads/test_board/settings
  TE::WORKSPACE_HSI_PATH:   /home/luca/Downloads/test_board/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/luca/Downloads/test_board/workspace/sdk
  TE::LIB_PATH:             /home/luca/Downloads/test_board/sw_lib
  TE::SCRIPT_PATH:          /home/luca/Downloads/test_board/scripts
  TE::DOC_PATH:             /home/luca/Downloads/test_board/doc
  TE::PREBUILT_BI_PATH:     /home/luca/Downloads/test_board/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/luca/Downloads/test_board/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/luca/Downloads/test_board/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/luca/Downloads/test_board/prebuilt/os
  TE::PREBUILT_EXPORT_PATH: /home/luca/Downloads/test_board/../export
  TE::LOG_PATH:             /home/luca/Downloads/test_board/v_log
  TE::BACKUP_PATH:          /home/luca/Downloads/test_board/backup
  TE::ZIP_PATH:             /usr/bin/zip
  TE::SDSOC_PATH:           /home/luca/Downloads/test_board/../SDSoC_PFM
  TE::ADD_SD_PATH:          /home/luca/Downloads/test_board/misc/sd
  TE::TMP_PATH:             /home/luca/Downloads/test_board/tmp
  TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 2
INFO:(TE) Parameter Option: --gui
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 4
INFO:(TE) Parameter Option: --clean
INFO:(TE) Parameter Option Value: 2
INFO:(TE) Parameter Index: 6
INFO:(TE) Parameter Option: --boardpart
INFO:(TE) Parameter Option Value: 22
-----------------------------------------------------------------------
INFO: [TE_INIT-129] Run TE::INIT::run_project 22 1 1 2
INFO: [TE_INIT-182] Source /home/luca/Downloads/test_board/settings/design_settings.tcl.
INFO: [TE_INIT-0] Script Info:
  Vivado Version:                             Vivado v2019.2 (64-bit)
  TE Script Version:                          2019.2.3
  Board Part (Definition Files) CSV Version:  1.4
  Software IP CSV Version:                    2.3
  Board Design Modify CSV Version:            1.1
  ZIP ignore CSV Version:                     1.0
  ---
  Start project with:                         NA
  ------
INFO: [TE_INIT-1] Script Environment:
  Vivado Setting:     1
  LabTools Setting:   0
  SDK Setting:        1
  SDSOC Setting:      0
  ------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           test_board
  TE::VPROJ_PATH:           /home/luca/Downloads/test_board/vivado
  TE::VLABPROJ_PATH:        /home/luca/Downloads/test_board/vivado_lab
  TE::BOARDDEF_PATH:        /home/luca/Downloads/test_board/board_files
  TE::FIRMWARE_PATH:        /home/luca/Downloads/test_board/firmware
  TE::IP_PATH:              /home/luca/Downloads/test_board/ip_lib
  TE::BD_PATH:              /home/luca/Downloads/test_board/block_design
  TE::XDC_PATH:             /home/luca/Downloads/test_board/constraints
  TE::HDL_PATH:             /home/luca/Downloads/test_board/hdl
  TE::SET_PATH:             /home/luca/Downloads/test_board/settings
  TE::WORKSPACE_HSI_PATH:   /home/luca/Downloads/test_board/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/luca/Downloads/test_board/workspace/sdk
  TE::LIB_PATH:             /home/luca/Downloads/test_board/sw_lib
  TE::SCRIPT_PATH:          /home/luca/Downloads/test_board/scripts
  TE::DOC_PATH:             /home/luca/Downloads/test_board/doc
  TE::PREBUILT_BI_PATH:     /home/luca/Downloads/test_board/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/luca/Downloads/test_board/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/luca/Downloads/test_board/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/luca/Downloads/test_board/prebuilt/os
  TE::PREBUILT_EXPORT_PATH: /home/luca/Downloads/test_board/../export
  TE::LOG_PATH:             /home/luca/Downloads/test_board/v_log
  TE::BACKUP_PATH:          /home/luca/Downloads/test_board/backup
  TE::ZIP_PATH:             /usr/bin/zip
  TE::SDSOC_PATH:           /home/luca/Downloads/test_board/../SDSoC_PFM
  TE::ADD_SD_PATH:          /home/luca/Downloads/test_board/misc/sd
  TE::TMP_PATH:             /home/luca/Downloads/test_board/tmp
  TE::XILINXGIT_DEVICETREE: /home/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
INFO: [TE_INIT-16] Read board part definition list (File /home/luca/Downloads/test_board/board_files/TE0820_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: /home/luca/Downloads/test_board/sw_lib/apps_list.csv).
INFO: (TE_INIT-??) Software Definition CSV version passed
INFO: (TE_INIT-??) Software Definition CSV Version analyze platform table header
INFO: (TE_INIT-??) Software Definition CSV Version analyze bsp table header
INFO: (TE_INIT-??) Software Definition CSV Version analyze app table header
INFO: [TE_INIT-22] Read ZIP ignore list (File: /home/luca/Downloads/test_board/sw_lib/apps_list.csv).
INFO: [TE_UTIL-70] /home/luca/Downloads/test_board/vivado was deleted.
Found ID: 22
Board part csv name check:  22 is unique on position 0.
INFO: [TE_INIT-4] Board Part definition:
  TE::ID:             22
  TE::PRODID:         TE0820-03-03EG-1EL
  TE::PARTNAME:       xczu3eg-sfvc784-1-e
  TE::BOARDPART:      trenz.biz:te0820_3eg_1e:part0:2.0
  TE::SHORTDIR:       3eg_1e_2gb
  TE::ZYNQFLASHTYP:   qspi-x8-dual_parallel
  TE::FPGAFLASHTYP:   mt25qu512-qspi-x8-dual_parallel
  TE::PCB_REV:        REV03
  TE::DDR_SIZE:       2GB
  TE::FLASH_SIZE:     128MB
  TE::EMMC_SIZE:      4GB
  TE::OTHERS:         2.5 mm connectors
  TE::NOTES:          NA
  ------
Generate new project (Path: /home/luca/Downloads/test_board/vivado).
INFO: [TE_INIT-69] Set Board Definition path: /home/luca/Downloads/test_board/board_files
ERROR: [TE_INIT-145] Script (TE::VIV::create_project) failed: ERROR: [Project 1-848] Could not get a valid part for the project. Make sure you have the required part installed, use the get_parts command to see the list of valid parts.
.
ERROR: (TE_INIT-145) Script (TE::VIV::create_project) failed: ERROR: [Project 1-848] Could not get a valid part for the project. Make sure you have the required part installed, use the get_parts command to see the list of valid parts.
.
ERROR:(TE) Script (TE::INIT::run_project) failed: .
ERROR:(TE) Script (TE::main) failed: .
INFO: [Common 17-206] Exiting Vivado at Tue Feb 11 15:23:44 2020...
-------------------------scripts finished----------------------------
--------------------------------------------------------------------
--------------------Change to design folder-------------------------
------------------------Design finished-----------------------------

Any idea?

Edit: I actually saw this quite neat feature of board repositories https://github.com/Xilinx/XilinxBoardStore , wondering if updating those could be a viable solution? (They don't have the TE0820 module with 2GB DDR), although I believe the scripts would still be needed to add the option to generate a custom FSBL

/Luca
« Last Edit: February 11, 2020, 08:40:06 AM by luca_osrf »

JH

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Re: TE0820 - 2019.2 Reference design - create_project failed
« Reply #1 on: February 11, 2020, 10:42:19 AM »
Hi,
did you install all device with your Vivado/Vitis installation?
Can you upen your Vivado and check if you can select "xczu3eg-sfvc784-1-e"
br
John

luca_osrf

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Re: TE0820 - 2019.2 Reference design - create_project failed
« Reply #2 on: February 12, 2020, 03:08:23 AM »
Hi John!

That was indeed the issue, creating a project with the part also failed, could find the solution in installing the 7 series support even though we are not using it, following the Xilinx forums https://forums.xilinx.com/t5/Design-Entry/Vivado-2019-2-issue-to-create-Block-Design/td-p/1041271

Thanks!
/Luca

JH

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Re: TE0820 - 2019.2 Reference design - create_project failed
« Reply #3 on: February 12, 2020, 10:52:05 AM »
use "Xilinx Information Center" (which is normaly installed with your Vivado/Vitis version).
Got to "Manage Installs" tab and press button "Add Toos/Devices" for your Vitis version
br
John