Updating HW config for SDx

[Henry]

Hello,

first I would like to say I am very new to the Vivado environment so sorry if my questions are very elementary.

I downloaded the github repository and I could build the FOC template in SDx IDE and put it on the SD card without issues.
However after opening the HW vivado project folder in Vivado 2017.1 it reported that some IP blocks needed updating. I ran report_ip_status and updated the blocks and then re-validated the block design.

Now when I started a new FOC template project it fails to build with the following message:

ERROR: [BD 5-336] This command cannot be run, as the BD-design is locked. Locked reason(s):
See C:/Workspace/my_foc_1/Debug/_sds/p0/ipi/vivado.log for the context of the Vivado message above.
* BD design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue.
List of locked IPs:
zsys_proc_sys_reset_0_0
zsys_proc_sys_reset_0_1
zsys_proc_sys_reset_0_2
zsys_axis_subset_converter_0_0
zsys_proc_sys_reset_3_0

but now running report_IP_status states that there are no IP issues.

Code: [Select]

+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| zsys_proc_sys_reset_0_0        | Up-to-date | No changes required |  *(8)     | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z010clg400-1      |
|                                |            |                     |           | Reset              | (Rev.   |               |            |                      |
|                                |            |                     |           |                    | 11)     |               |            |                      |
+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| zsys_proc_sys_reset_0_1        | Up-to-date | No changes required |  *(9)     | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z010clg400-1      |
|                                |            |                     |           | Reset              | (Rev.   |               |            |                      |
|                                |            |                     |           |                    | 11)     |               |            |                      |
+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| zsys_proc_sys_reset_0_2        | Up-to-date | No changes required |  *(10)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z010clg400-1      |
|                                |            |                     |           | Reset              | (Rev.   |               |            |                      |
|                                |            |                     |           |                    | 11)     |               |            |                      |
+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| zsys_proc_sys_reset_3_0        | Up-to-date | No changes required |  *(11)    | Processor System   | 5.0     | 5.0 (Rev. 11) | Included   | xc7z010clg400-1      |
|                                |            |                     |           | Reset              | (Rev.   |               |            |                      |
|                                |            |                     |           |                    | 11)     |               |            |                      |
+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| zsys_axis_subset_converter_0_0 | Up-to-date | No changes required |  *(5)     | AXI4-Stream Subset | 1.1     | 1.1 (Rev. 12) | Included   | xc7z010clg400-1      |
|                                |            |                     |           | Converter          | (Rev.   |               |            |                      |
|                                |            |                     |           |                    | 12)     |               |            |                      |
+--------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+

what steps do I need to take to get past this issue?

A second question about the design of the FOC project, I was wondering why PWM and Angle_Encoder exist as PI blocks and not written as part of the SCSoc Project that would output through the rx_fifo or tx_fifo and then to board I/O?

Regards

Henry

[Oleksandr Kiyenko]

Hello,

unfortunately, Vivado 2017.1 and "internal" Vivado 2017.1 which included in SDx are slightly different and have different versions of IPs.
You need to run Vivado which included in SDx. Should be in a path like C:\Xilinx\SDx\%Version%\Vivado
There are no icons on the desktop or in the start menu for this version (as it supposed to be "for internal use"), so you need to navigate to it in explorer and run it.

Best regards
Oleksandr Kiyenko

[Henry]

Thanks for the reply Oleksandr Kiyenko

Vivado 2017.1 that was hidden away did solve my issues.

any chance you could shed some light on my second question?
Why do PWM and Angle_Encoder exist as PI blocks and not written as part of the SCSoc Project?

Regards

Henry

[Oleksandr Kiyenko]

Hi Henry,

your question is not 100% clear for me, but I'll try to answer.
As I remember this IP core is VHDL code which packed as IP and added to the ip_lib folder of the platform. It's not C code and used as input/output interface in the main code.

BR
Oleksandr

[Henry]

Sorry,

let me try again  .

My question is why does the PWM IP block exist?
What is preventing the function of the PWM block to exist within the my_foc C function?

I assume it is to do with the clocking of the different blocks / functions within the system but I am not too sure and would like to have some understanding of these design choices.

Thanks once again.

Regards

Henry

[Oleksandr Kiyenko]

Hi Henry,

yes, it's possible to implement this function in HLS code, but there are 2 reasons not to do that.
1. Keep all interfaces similar and not much "hardware-specific"
2. If the PWM function will be implemented wrong, (that is more than possible) you will burn the board.

BR
Oleksandr

[ssysheldon1]

I have a question about whether we can use c language to program PWM and Angle_Encoder instead of useing VHDL or verliog?

[Oleksandr Kiyenko]

Hello,

Don't understand your question. This project already uses C language to generate input data for the PWM core.
If you want to implement PWM on C it's possible, but please read my previous answer why it was not done.

Best regards
Oleksandr Kiyenko

[ssysheldon1]

Need help,thanks four your help.
1.Do you have Linux source code or Where can I download the Linux source code?
 2.Can I change the interface of the web UI?for examples  adding new monitor variables or adding buttons to change the PID value;
thanks