TE0808 Starter Board with petalinux 2017.3?

[Aaron]

I'm trying to get my software running on the TE0808 starter board.  For various reasons, I'm required to build with 2017.3 petalinux.  I recognize the latest wiki documentation suggests 2018.2, so I know I can't use those build steps (is that true?)

I was able to find a webpage full of StarterKit downloads. 

https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/Reference_Design

There is a 2017.2 and a 2017.4, but no 2017.3, which is what I'm using.

With no documentaiton, I just guessed that I should download the one for 2017.2 run the init_config.sh in the os/petalinux directory, then built the image with 2017.3 using petalinux-config --get-hw-description and petalinux-build.

This image fails to boot.  Essentially, it says the kernel image is too large ("increase CONFIG_SYS_BOOTM_LEN").  This is a symbol in project-spec/meta-user/recipes-bsp/u-boot/files/platform-top.h in the 2018.2 version, but this symbol is not present in the 2017.2 version I've downloaded.

Should I be using the 2017.4?  Should I be doing something else?   I guess I could just try various versions until I find one that works(?)

Any help or pointers to documentation that I might have missed, would be greatly appreciated.

[JH]

Hi,
unfortunately we can't support all vivado version.s in the most cases we update even numbers of vivado. Depending on Xilinx changes, sometimes also odd.

If sources works with other Xilinx version depends on changes done by xilinx.

I've put an PDF version of the 2017.2 and 2017.4 starterkit design online, so you can use also this documentation.  --> need appr.1 h to be availablr

For UltraScale+ Zynq I would recommend to use  Vivado 2018.2 or 17.4. During this version Xilinx has changed a lot on FSBL, PMU...

In case you would still use 2017.3, you can try following:
1. Create new project with 2017.4 board part files and start board automation for ZynqMP IP
2. export HDF generate FSBL and add changes from our 2017.4 template to this one --> all changes labled with comment "TE MOD"
3. create new petalinux project with your HDF and add all changes we have done manually --> see PDF documentation
4. create Boot.bin with your modified FSBL, bitfile and uboot.elf

But you must try out, I can't give more support fur this older vivado version.
br
John

[Aaron]

Thank you.  I will use 2017.2

I assume I won't be able to use the petalinux build tips at https://wiki.trenz-electronic.de/display/PD/TE0808+StarterKit#space-menu-link-content, correct?  I assume those are specific to 2018.2

Instead, I found TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip.  I found no documentation, but I did what was intuitive (ran the script) and got something that boots despite an exception in zynqmp_pll_set_rate during boot (which apparently isn't fatal).

After I ran the init_config.sh script, to configure this petalinux workspace, I used a prebuilt HDF file in the prebuilt/hardware/9eg_2ib_sk/ directory ("petalinux-config --^Ct-hw-description=../../prebuilt/hardware/9eg_2ib_sk/").  Could that have contributed to the exception?

I have no idea which of the prebuilt/hardware directories I should be getting my HDF file out of, or whether indeed I should be using the "petalinux-config --get-hw-description" command in this pregenerated build directory.

Could I get guidance on this?  If I need to use a prebuilt HDF file, then how can I identify the HDF that I need for the starter kit?  All I see on the TE0808 SOM is "TE0808-04" and all I see on the carrier board in the starter kit is "TEBF 0808-04A".  I have no idea which of the prebuilt ultrascale hardware directories this corresponds to:  "9eg_1ea_sk", "9eg_1eb_sk", or "9eg_2ib_sk".. or some of the other ones?

[JH]

Hi,
https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0808/Reference_Design/2017.2/StarterKit
---> TE0808-StarterKit-vivado_2017.2-build_07-v2.pdf  is 17.2 version of the Wiki documentation

page 6 chapter  Hardware Requirements is a table with Articel numbers, which will be supported and corresponding Board Part short dir name:
So which assembly version did you bought? Can you give me the articel number from your order? If you are not sure, send me the serial number of the module.

At first try out prebuilt boot.bin and image.ub. Then start to generate all by yourself.
For petalinux we  has also an history with general  notes on our wiki: https://wiki.trenz-electronic.de/display/PD/PetaLinux+KICKstart#PetaLinuxKICKstart-PetaLinux2017.2

br
John

[Aaron]

Thank you, that was very helpful.  Luckily I still have the box my starter kit came in, and I was able to find a part number on a sticker on the box (it's too bad there was no sticker on the printed circuit board).  Page 6 then directed me to the correct hdf file.

The StarterKit documentation is very helpful.  However, I have a few questions about the section on page 21 of the TE StarterKit document, v.27.  In the section "Additional Software", with subsection "SI5345".:

• Is this procedure with ClockBuilder required or optional?  I would tend to imagine this is optional, and I would suggest the documentation be changed to indicate that.
• When exporting header files from ClockBuilder, should one select "Include pre- and post-write control register writes"?  I would suggest the documentation be updated to indicate whether this is important, and if so, which selection should be made

Without doing the ClockBuilder procedure (again, I assume it's optional because one would assume that the StarterKit would be shipped with functional header files for the FSBL), I get a petalinux image that gets an error at boot:

Code: [Select]

[    3.335488] xilinx-dp-snd-pcm amba:dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[    3.343183] PLL: enable
[    3.345738] PLL: shutdown
[    3.348940] Two devices are using vpll which is forbidden
[    3.354294] ------------[ cut here ]------------
[    3.358870] WARNING: CPU: 0 PID: 1 at /expanse/aaron/StarterKit_2017.2/os/petalinux/build/tmp/work-shared/plnx_aarch64/kernel-source/drivers/clk/zynqmp/pll.c:190 zynqmp_pll_set_rate+0x200/0x220
[    3.376064] Modules linked in:
[    3.379080]
[    3.380560] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.9.0-xilinx-v2017.2 #1
[    3.387678] Hardware name: xlnx,zynqmp (DT)
[    3.391844] task: ffffffc87b876c00 task.stack: ffffffc87b878000
[    3.397748] PC is at zynqmp_pll_set_rate+0x200/0x220
[    3.402694] LR is at zynqmp_pll_set_rate+0x200/0x220
[    3.407641] pc : [<ffffff8008459898>] lr : [<ffffff8008459898>] pstate: 60000045
[    3.415025] sp : ffffffc87b87bb20
[    3.418316] x29: ffffffc87b87bb20 x28: 0000000000000000
[    3.423609] x27: ffffff8008c5df18 x26: ffffff8008d23000
[    3.428904] x25: 0000000001588800 x24: 0000000000000000
[    3.434198] x23: ffffffc87b01a410 x22: ffffffc87ba94100
[    3.439493] x21: 0000000001fca055 x20: 0000000001fca055
[    3.444788] x19: 000000005ad20000 x18: 0000000000000010
[    3.450083] x17: 0000000000000000 x16: 0000000000000000
[    3.455377] x15: 0000000000000006 x14: ffffff8088d281d7
[    3.460672] x13: ffffff8008d281e5 x12: 000000000000011d
[    3.465967] x11: ffffffc87b87b880 x10: 000000000000011e
[    3.471262] x9 : 000000000000003d x8 : 2073692068636968
[    3.476557] x7 : 77206c6c70762067 x6 : ffffff8008d28214
[    3.481851] x5 : ffffff800843f290 x4 : 0000000000000000
[    3.487146] x3 : 0000000000000000 x2 : 000000000000065e
[    3.492441] x1 : ffffff8008caa9c8 x0 : 000000000000002d
[    3.497735]
[    3.499215] ---[ end trace eaffecdd361a5105 ]---
[    3.503814] Call trace:
[    3.506246] Exception stack(0xffffffc87b87b950 to 0xffffffc87b87ba80)
[    3.512671] b940:                                   000000005ad20000 0000008000000000
[    3.520490] b960: ffffffc87b87bb20 ffffff8008459898 ffffff8008d2a5f8 000000000000002d
[    3.528302] b980: ffffffc87b87b9a0 ffffff80080d908c ffffff8008d27c68 ffffff8008ac5b48
[    3.536114] b9a0: ffffffc87b87ba40 ffffff80080d9364 000000005ad20000 0000000001fca055
[    3.543926] b9c0: 0000000001fca055 ffffffc87ba94100 ffffffc87b01a410 0000000000000000
[    3.551738] b9e0: 0000000001588800 ffffff8008d23000 000000000000002d ffffff8008caa9c8
[    3.559550] ba00: 000000000000065e 0000000000000000 0000000000000000 ffffff800843f290
[    3.567362] ba20: ffffff8008d28214 77206c6c70762067 2073692068636968 000000000000003d
[    3.575174] ba40: 000000000000011e ffffffc87b87b880 000000000000011d ffffff8008d281e5
[    3.582986] ba60: ffffff8088d281d7 0000000000000006 0000000000000000 0000000000000000
[    3.590798] [<ffffff8008459898>] zynqmp_pll_set_rate+0x200/0x220
[    3.596782] [<ffffff80084545d0>] clk_change_rate+0x1e0/0x238
[    3.602423] [<ffffff8008454688>] clk_core_set_rate_nolock+0x60/0xc8
[    3.608673] [<ffffff8008454718>] clk_set_rate+0x28/0x58
[    3.613881] [<ffffff8008722bf8>] xilinx_dp_codec_probe+0xd8/0x1e8
[    3.619959] [<ffffff8008502430>] platform_drv_probe+0x58/0xc0
[    3.625686] [<ffffff80085008d4>] driver_probe_device+0x1fc/0x2a8
[    3.631675] [<ffffff8008500a2c>] __driver_attach+0xac/0xb0
[    3.637143] [<ffffff80084fe924>] bus_for_each_dev+0x64/0xa0
[    3.642698] [<ffffff80085000c0>] driver_attach+0x20/0x28
[    3.647992] [<ffffff80084ffc10>] bus_add_driver+0x110/0x230
[    3.653548] [<ffffff8008501210>] driver_register+0x60/0xf8
[    3.659017] [<ffffff8008502368>] __platform_driver_register+0x40/0x48
[    3.665442] [<ffffff8008c40cb0>] xilinx_dp_codec_driver_init+0x18/0x20
[    3.671952] [<ffffff80080830b8>] do_one_initcall+0x38/0x128
[    3.677507] [<ffffff8008c10c94>] kernel_init_freeable+0x140/0x1e0
[    3.683582] [<ffffff8008932fc8>] kernel_init+0x10/0x100
[    3.688788] [<ffffff8008082e80>] ret_from_fork+0x10/0x50
[    3.694217] Write failed to divider address:fd1a007c
[    3.699372] PLL: enable
[    3.701896] xilinx-dp-snd-codec amba:dp_snd_codec0: Xilinx DisplayPort Sound Codec probed
[    3.710371] xilinx-dp-snd-card amba:dp_snd_card: xilinx-dp-snd-codec-dai <-> xilinx-dp-snd-codec-dai mapping ok

Note that this did not occur with the premade 2018.2 boot image on the SD card, but it does occur with the prebuilt images in the Starter Kit - \prebuilt\boot_images\9eg_1eb_sk\u-boot\BOOT.bin and prebuilt\os\petalinux\9eg_1ea_sk\image.ub (note that there is no prebuilt 9eg_1eb_sk\image.ub)
 
I traced the error down to a WARN statement in https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2017.2/drivers/clk/zynqmp/pll.c, where it warns that two devices can't use the same clock:

Code: [Select]

/*
* We're running on a ZynqMP compatible machine, make sure the
* VPLL only has one child.
*/
children = clk_get_children("vpll");

/* Account for vpll_to_lpd and dp_video_ref */
if (children > 2)
WARN(1, "Two devices are using vpll which is forbidden\n");

I have no idea what is causing this issue, why it does not occur in 2018.2, or how important it is.

[JH]

Hi,

    Is this procedure with ClockBuilder required or optional?  I would tend to imagine this is optional, and I would suggest the documentation be changed to indicate that.
    When exporting header files from ClockBuilder, should one select "Include pre- and post-write control register writes"?  I would suggest the documentation be updated to indicate whether this is important, and if so, which selection should be made

Reference Design is one of endless possible configurations of the ZynqMP. If this default configuration of the SI is ok for you than this section is otional.

There is a design flow section, with basic steps to reproduce the design. SI reprogramming is not a part of them.

Note that this did not occur with the premade 2018.2 boot image on the SD card, but it does occur with the prebuilt images in the Starter Kit - \prebuilt\boot_images\9eg_1eb_sk\u-boot\BOOT.bin and prebuilt\os\petalinux\9eg_1ea_sk\image.ub (note that there is no prebuilt 9eg_1eb_sk\image.ub)

See Section Design Flow: Step 7
"
Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
"prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise
"prebuilt\os\petalinux\default"
"
So if ""prebuilt\os\petalinux\<short name>\9eg_1eb_sk\image.ub" is not available use "prebuilt\os\petalinux\default"

I have no idea what is causing this issue, why it does not occur in 2018.2, or how important it is.

https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264#Vivado/SDK/SDSoC-XilinxSoftware-ProductUpdateReleaseNotesandKnownIssues
https://wiki.trenz-electronic.de/pages/viewpage.action?pageId=14746264#Vivado/SDK/SDSoC-XilinxDevices-Erratasandsolutions


br
John

[Aaron]

I was able to build an image from scratch. and have it boot from the SD card.  My particular problem was I had files left over from petalinux 2017.3 that were making the build unhappy.  The solution was to delete the components, build, and meta-plnx-generated directories (the last of these three is never deleted by anything that any petalinux command does, so it has to be manually deleted).