Author Topic: MAX10 ADC channel numbering  (Read 2064 times)

ossmann@fh-aachen.de

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MAX10 ADC channel numbering
« on: October 26, 2018, 05:23:16 PM »
It seems that I have to use

channel No 02 in order to access J1-pin2 AIN0=ADC1IN8 FPGA pin E1
channel No 06 in order to access J1-pin3 AIN1=ADC1IN2 FPGA pin C2

Where is the correspondnce FPGA-pin / ADC channel number documented?


philippe69

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Re: MAX10 ADC channel numbering
« Reply #2 on: January 26, 2021, 09:08:21 PM »
Hello,
I have a correspondance channel ADC issue. Could you please help me ?

Even if i write a sequencer or i use the modular_ADC_core sequencer, the channels i use are changing with the IP bloc params.
It's my problem and i don't understand why.
Example :
Select 8 slots, affected to 8 channels : slot1 to ch1.... slot 8 to ch8.
But I have AIN1 to ch3, AIN2 to CH6 and so on !!
 
I wrote a avalon Master sequencer in SpeedTest Sequenceur\avalon_ADC\avalon_ADC.v
The program top.v does nothing but call the adc design in qsys.
The output registers are used to inspect the adc output data_ADC with the signa tap logic analyzer.

Find enclosed my little code.
Thank's for help
Philippe

Thomas D

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Re: MAX10 ADC channel numbering
« Reply #3 on: January 27, 2021, 09:07:15 AM »
Hi,
did you note the pin assignment in the schematics?
For pin assignment between the channels and the FPGA pins you have to look here https://www.intel.com/content/www/us/en/programmable/documentation/sam1393576011848.html#sam1424951587370 and in the schematics (see screenshot for example).
TEI0001-03-08-C8 example: CH1 -> ADC1IN1 -> AIN3 (Pin D1)

br
Thomas

philippe69

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Re: MAX10 ADC channel numbering
« Reply #4 on: February 07, 2021, 06:36:55 PM »
Thank's a lot
Philippe