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Started by charlie5902, October 17, 2018, 05:36:50 PM
QuoteThis is starting to sound a lot like flaky PLL operation in the Starter Kit configuration.
Quotethe Start Kit projects that worked at end of day yesterday do not work this morning
QuoteMy test board projects still work
Quote1. At this point, the only thing that that does not work is the stock Starter Kit project plus AXI Gpio and ILA, using bare metal Xilinx SDK and a sdk-generated Hello World project. The init script generated by the SDK appears to incorrectly configure the PL clock PLLs, which causes the issues I described. This Starter Kit PL clock issue happens on 2 identical Trenz Carrier/SOM dev platforms.
Quote2. My thought is that with Petalinux and FSBL this issue may not exist. We are going to be moving to Petalinux soon.
Quote3. My current Vivado project has a working PLL configuration. It was generated from a Starter Kit as baseline but has Carrier stuff stripped out.
Quote4. As we are evaluating this platform for eventual use in final product, we would like to be confident there are no risk issues with the hardware. To that end, it would be really helpful to have a Starter Kit project that runs correctly with an XSDK simple Hello World project that does not have PL Clock PLL issues. Any thoughts you have on making this happen would be greatly appreciated.
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