TE0803-03-3EG-1A-S Starter Kit Vivado 2017.1 reference design to Vivado 2017.4

[jlamp]

Hi all,

I am trying to export Vivado 2017.1 TE0803-03-3EG-1A-S Starter Kit reference design to a newer Vivado 2017.4 but I am having issues between the processor and the axis_live_audio IP core regarding to the clock and I am not able to generate the bitstream. This is the error log I am having:

Code: [Select]

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /zynq_ultra_ps_e_0/S_AXIS_AUDIO(25000000) and /axis_live_audio_0/m_axis(100000000)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /zynq_ultra_ps_e_0/S_AXIS_AUDIO(zusys_zynq_ultra_ps_e_0_0_dp_audio_ref_clk) and /axis_live_audio_0/m_axis(zusys_zynq_ultra_ps_e_0_0_pl_clk0)
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axis_live_audio_0/s_axis(100000000) and /zynq_ultra_ps_e_0/M_AXIS_MIXED_AUDIO(25000000)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /axis_live_audio_0/s_axis(zusys_zynq_ultra_ps_e_0_0_pl_clk0) and /zynq_ultra_ps_e_0/M_AXIS_MIXED_AUDIO(zusys_zynq_ultra_ps_e_0_0_dp_audio_ref_clk)
WARNING: [BD 41-927] Following properties on pin /SC0808BF_0/sys_clock have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
    CLK_DOMAIN=zusys_zynq_ultra_ps_e_0_0_pl_clk1
ERROR: [BD 41-1031] Hdl Generation failed for the IP Integrator design /home/jlamperez/Proyectos/Trenz_TE0803_and_TE0808/Vivado/2017.1/StarterKit/vivado/StarterKit.srcs/sources_1/bd/zusys/zusys.bd
ERROR: [Common 17-39] 'make_wrapper' failed due to earlier errors.

Can someone give me some help?

Thank you very much!

[Oleksandr Kiyenko]

Hello.
Vivado 2017.1 have bug M_AXIS_MIXED_AUDIO bus don't associated with dp_audio_ref_clk so I have to make in axis_live_audio core "fake" axis_aclk clock, which is not really used and connect real clock to ref_clk_in.
Looks like this bug was fixed in 2017.4. You can try to disconnect axis_aclk from pl_clk0 100 MHz clock and connect both axis_aclk and ref_clk_in to dp_audio_ref_clk.

Best regards
Oleksandr Kiyenko

[jlamp]

Hi Oleksandr,

I was able to generate bitstream disconnecting axis_aclk from pl_clk0 100 MHz clock and connecting both axis_aclk and ref_clk_in to dp_audio_ref_clk.

Regards,
Jorge