Hi,
you can change the DDR settings, like that one the screenshot at the attachment. Regenerate bitfiles, fsbl and boot.bin with this settings. A other customer has send us this configuration for ES1. DDR will be slower like on older Vivado Designs, but it should work. It seems is something wrong with higher speed, which is not checked by xilinx default ddr test.
I will generate new boart part files and update reference design during next week. We found also some new PS settings on Vivado 2017.1 ZynqMP IP (they wasn't available on 16.4), which are default not correct. So I would recommend to use our new board parts after my update.
br
John