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Author Topic: TEBE0808 2016.4 Vivado script_main.tcl error  (Read 14280 times)

adamdunc

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TEBE0808 2016.4 Vivado script_main.tcl error
« on: March 10, 2017, 04:04:20 AM »
Hi,

I am getting an error when running the TEBF0808 2016.4 script_main.tcl in Vivado 2016.4 in Ubuntu 16.04

I am following the steps from Option 2 at https://wiki.trenz-electronic.de/display/PD/Vivado+Projects

I was able to run the TEBF0808 2016.3 script just fine in Vivado 2016.3. Do you know if anything has changed in 2016.4?

Here is the specific command I am issuing for step 5 in https://wiki.trenz-electronic.de/display/PD/Vivado+Projects
src ../scripts/script_main.tcl  --run 1 --gui 1 --clean 2 --boardpart TE0808-ES1

My output is listed below

-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           Carrier_TEBF0808
  TE::VPROJ_PATH:           /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado
  TE::VLABPROJ_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado_lab
  TE::BOARDDEF_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/board_files
  TE::FIRMWARE_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/firmware
  TE::IP_PATH:              /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/ip_lib
  TE::BD_PATH:              /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/block_design
  TE::XDC_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints
  TE::HDL_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/hdl
  TE::SET_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/settings
  TE::WORKSPACE_HSI_PATH:   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/workspace/sdk
  TE::LIB_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sw_lib
  TE::SCRIPT_PATH:          /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/scripts
  TE::DOC_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/doc
  TE::PREBUILT_BI_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/os
  TE::LOG_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/v_log
  TE::BACKUP_PATH:          /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/backup
  TE::ZIP_PATH:             
  TE::SDSOC_PATH:           /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sdsoc
  TE::XILINXGIT_DEVICETREE: 
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 2
INFO:(TE) Parameter Option: --gui
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 4
INFO:(TE) Parameter Option: --clean
INFO:(TE) Parameter Option Value: 2
INFO:(TE) Parameter Index: 6
INFO:(TE) Parameter Option: --boardpart
INFO:(TE) Parameter Option Value: TE0808-ES1
-----------------------------------------------------------------------
INFO: [TE_INIT-129] Run TE::INIT::run_project TE0808-ES1 1 1 2
INFO: [TE_INIT-0] Script Info:
  Vivado Version:                             Vivado v2016.4 (64-bit)
  TE Script Version:                          2016.4.03
  Board Part (Definition Files) CSV Version:  1.2
  Software IP CSV Version:                    1.9
  Board Design Modify CSV Version:            1.1
  ZIP ignore CSV Version:                     1.0
  ---
  Start project with:                         NA
  ------
INFO: [TE_INIT-1] Script Environment:
  Vivado Setting:     0
  LabTools Setting:   0
  SDK Setting:        0
  SDSOC Setting:      0
  ------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           Carrier_TEBF0808
  TE::VPROJ_PATH:           /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado
  TE::VLABPROJ_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado_lab
  TE::BOARDDEF_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/board_files
  TE::FIRMWARE_PATH:        /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/firmware
  TE::IP_PATH:              /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/ip_lib
  TE::BD_PATH:              /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/block_design
  TE::XDC_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints
  TE::HDL_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/hdl
  TE::SET_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/settings
  TE::WORKSPACE_HSI_PATH:   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/workspace/sdk
  TE::LIB_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sw_lib
  TE::SCRIPT_PATH:          /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/scripts
  TE::DOC_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/doc
  TE::PREBUILT_BI_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/software
  TE::PREBUILT_OS_PATH:     /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/prebuilt/os
  TE::LOG_PATH:             /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/v_log
  TE::BACKUP_PATH:          /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/backup
  TE::ZIP_PATH:             
  TE::SDSOC_PATH:           /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sdsoc
  TE::XILINXGIT_DEVICETREE: 
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
INFO: [TE_INIT-16] Read board part definition list (File /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/board_files/TE0808_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sw_lib/apps_list.csv).
INFO: [TE_INIT-22] Read ZIP ignore list (File: /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/sw_lib/apps_list.csv).
INFO: [TE_UTIL-56] /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado was deleted.
ID not found for TE0808-ES1 0, return default: NA
Found ID: 2
Board part csv name check:  2 is unique on position 0.
INFO: [TE_INIT-4] Board Part definition:
  TE::ID:             2
  TE::PRODID:         TE0808-ES1
  TE::PARTNAME:       xczu9eg-ffvc900-1-i-es1
  TE::BOARDPART:      trenz.biz:te0808_es1:part0:1.0
  TE::SHORTDIR:       te0808_es1
  TE::ZYNQFLASHTYP:   qspi_dual_parallel
  TE::FPGAFLASHTYP:   NA
  ------
Generate new project (Path: /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado).
INFO: [TE_INIT-69] Set Board Definition path: /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/board_files
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2016.4/data/ip'.
INFO: [TE_INIT-70] Set IP path : /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/ip_lib
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/ip_lib'.
Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_io.xdc
 /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/vivado_target.xdc
 /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_bitgen.xdc
  ------
Set processing order normal for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_io.xdc
Set use for implementation only for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_io.xdc
Set processing order normal for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/vivado_target.xdc
Set use for synthesis and implementation for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/vivado_target.xdc
Set processing order normal for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_bitgen.xdc
Set use for implementation only for /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/constraints/_i_bitgen.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/block_design/zusys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zusys_bd
  TE::PR_TOPLEVELNAME: zusys_wrapper
  ------
  TE::IS_ZUSYS:        true
INFO: [TE_UTIL-2] Following block designs were found:
   /home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/block_design/zusys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0808_es2_tebf0808:part0:2.0, FPGA: xczu9eg-ffvc900-1-i-es2 at 2017-02-13T16:57:01.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD_TCL-3] Currently there is no design <zusys> in project, so creating one...
Wrote  : </home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado/Carrier_TEBF0808.srcs/sources_1/bd/zusys/zusys.bd>
INFO: [BD_TCL-4] Making design <zusys> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zusys".
INFO: [Ipptcl 7-1463] No Compatible Board Interface found. Board Tab not created in customize GUI
WARNING: [BD 5-235] No pins matched 'get_bd_pins zynq_ultra_ps_e_0/dp_aux_data_in'
WARNING: [BD 5-235] No pins matched 'get_bd_pins zynq_ultra_ps_e_0/dp_hot_plug_detect'
WARNING: [BD 5-235] No pins matched 'get_bd_pins zynq_ultra_ps_e_0/dp_aux_data_oe_n'
WARNING: [BD 5-235] No pins matched 'get_bd_pins zynq_ultra_ps_e_0/dp_aux_data_out'
WARNING: [BD 5-235] No pins matched 'get_bd_pins zynq_ultra_ps_e_0/pl_clk1'
WARNING: [BD 41-597] NET <zynq_ultra_ps_e_0_dp_aux_data_oe_n> has no source
WARNING: [BD 41-597] NET <zynq_ultra_ps_e_0_dp_aux_data_out> has no source
WARNING: [BD 41-597] NET <zynq_ultra_ps_e_0_pl_clk0> has no source
Wrote  : </home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado/Carrier_TEBF0808.srcs/sources_1/bd/zusys/zusys.bd>
Adding cell -- trenz.biz:user:SC0808BF:1.0 - SC0808BF_0
Adding cell -- xilinx.com:ip:proc_sys_reset:5.0 - proc_sys_reset_0
Adding cell -- xilinx.com:ip:vio:3.0 - vio_rgpio
Adding cell -- xilinx.com:ip:zynq_ultra_ps_e:2.0 - zynq_ultra_ps_e_0
Successfully read diagram <zusys> from BD file </home/adamdunc/TEBF0808_2016_4_ref/Carrier_TEBF0808/vivado/Carrier_TEBF0808.srcs/sources_1/bd/zusys/zusys.bd>
ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
/SC0808BF_0/sys_clock
/proc_sys_reset_0/slowest_sync_clk
/vio_rgpio/clk

ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR:(TE) Script (TE::INIT::run_project) failed: .
ERROR:(TE) Script (TE::main) failed: .

Thanks,
Adam 
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JH

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #1 on: March 10, 2017, 09:46:24 AM »
Hi,

please use: src ../scripts/script_main.tcl  --run 1 --gui 1 --clean 2 --boardpart te0808_es1_tebf0808

We add two different board parts for TE0808 on the reference design.
te0808_es1 -> PS initialization only DDR, QSPI, and uart. this works independent from TEBF0808
te0808_es1_tebf0808 -> PS initialization with all other basic periphery from TEBF0808


This was my mistake. I will recreate the design in this way, that the reference design starts with both board parts.

br
John
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JH

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #2 on: March 10, 2017, 10:13:37 AM »
Hi,

the new reference design (te0808-Carrier_TEBF0808-vivado_2016.4-build_05_20170310095604.zip) should be available  in appr. 1 hour.
Board Part TE0808-ES1 also works with this reference design (tebf0808 specific settings are include also in zusys_bd.tcl).

br
John
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adamdunc

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #3 on: March 10, 2017, 01:17:06 PM »
John,

I just tried your new reference design with "src ../scripts/script_main.tcl  --run 1 --gui 1 --clean 2 --boardpart te0808_es1_tebf0808" and my error was resolved.

Thanks for the prompt reply!
Adam
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gordonk

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #4 on: April 12, 2018, 11:23:10 PM »


Quote from: JH on March 10, 2017, 10:13:37 AM
Hi,

the new reference design (te0808-Carrier_TEBF0808-vivado_2016.4-build_05_20170310095604.zip) should be available  in appr. 1 hour.
Board Part TE0808-ES1 also works with this reference design (tebf0808 specific settings are include also in zusys_bd.tcl).

br
John

Hi,

I'm getting a similar error myself running on Vivado 2017.4

Based on vivado example: TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip

source ../scripts/script_main.tcl -mode batch -notrace -tclargs --run 1 --gui 0 --clean 2 --boardpart 22

Can this get fixed?

Thanks!
Gordon

#-----------------------------------------------------------
# Vivado v2017.4 (64-bit)
# SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017
# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
# Start of session at: Thu Apr 12 12:53:04 2018
# Process ID: 7736
# Current directory: C:/Projects/trendz/te0803/v_log
# Command line: vivado.exe -source ../scripts/script_main.tcl -mode batch -notrace -tclargs --run 1 --gui 0 --clean 2 --boardpart 22
# Log file: C:/Projects/trendz/te0803/v_log/vivado.log
# Journal file: C:/Projects/trendz/te0803/v_log\vivado.jou
#-----------------------------------------------------------
source ../scripts/script_main.tcl -notrace
-----------------------------------------------------------------------
INFO:(TE) Load Settings Script finished
INFO:(TE) Load environment script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Utilities script finished
INFO:(TE) Load Vivado script finished
INFO:(TE) Load Designs script finished
INFO:(TE) Load User Command scripts finished
INFO:(TE) Load SDSoC script finished
-----------------------------------------------------------------------
-----------------------------------------------------------------------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           te0803
  TE::VPROJ_PATH:           C:/Projects/trendz/te0803/vivado
  TE::VLABPROJ_PATH:        C:/Projects/trendz/te0803/vivado_lab
  TE::BOARDDEF_PATH:        C:/Projects/trendz/te0803/board_files
  TE::FIRMWARE_PATH:        C:/Projects/trendz/te0803/firmware
  TE::IP_PATH:              C:/Projects/trendz/te0803/ip_lib
  TE::BD_PATH:              C:/Projects/trendz/te0803/block_design
  TE::XDC_PATH:             C:/Projects/trendz/te0803/constraints
  TE::HDL_PATH:             C:/Projects/trendz/te0803/hdl
  TE::SET_PATH:             C:/Projects/trendz/te0803/settings
  TE::WORKSPACE_HSI_PATH:   C:/Projects/trendz/te0803/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   C:/Projects/trendz/te0803/workspace/sdk
  TE::LIB_PATH:             C:/Projects/trendz/te0803/sw_lib
  TE::SCRIPT_PATH:          C:/Projects/trendz/te0803/scripts
  TE::DOC_PATH:             C:/Projects/trendz/te0803/doc
  TE::PREBUILT_BI_PATH:     C:/Projects/trendz/te0803/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     C:/Projects/trendz/te0803/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     C:/Projects/trendz/te0803/prebuilt/software
  TE::PREBUILT_OS_PATH:     C:/Projects/trendz/te0803/prebuilt/os
  TE::LOG_PATH:             C:/Projects/trendz/te0803/v_log
  TE::BACKUP_PATH:          C:/Projects/trendz/te0803/backup
  TE::ZIP_PATH:             C:/Program Files/7-Zip/7z.exe
  TE::SDSOC_PATH:           C:/Projects/trendz/te0803/../SDSoC_PFM
  TE::TMP_PATH:             C:/Projects/trendz/te0803/tmp
  TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
-----------------------------------------------------------------------
INFO:(TE) Parameter Index: 0
INFO:(TE) Parameter Option: --run
INFO:(TE) Parameter Option Value: 1
INFO:(TE) Parameter Index: 2
INFO:(TE) Parameter Option: --gui
INFO:(TE) Parameter Option Value: 0
INFO:(TE) Parameter Index: 4
INFO:(TE) Parameter Option: --clean
INFO:(TE) Parameter Option Value: 2
INFO:(TE) Parameter Index: 6
INFO:(TE) Parameter Option: --boardpart
INFO:(TE) Parameter Option Value: 22
-----------------------------------------------------------------------
INFO: [TE_INIT-129] Run TE::INIT::run_project 22 1 0 2
INFO: [TE_INIT-0] Script Info:
  Vivado Version:                             Vivado v2017.4 (64-bit)
  TE Script Version:                          2017.4.07
  Board Part (Definition Files) CSV Version:  1.3
  Software IP CSV Version:                    2.0
  Board Design Modify CSV Version:            1.1
  ZIP ignore CSV Version:                     1.0
  ---
  Start project with:                         vivado_create_project_batchmode
  ------
INFO: [TE_INIT-1] Script Environment:
  Vivado Setting:     1
  LabTools Setting:   0
  SDK Setting:        1
  SDSOC Setting:      0
  ------
INFO: [TE_INIT-3] Initial project names and paths:
  TE::VPROJ_NAME:           te0803
  TE::VPROJ_PATH:           C:/Projects/trendz/te0803/vivado
  TE::VLABPROJ_PATH:        C:/Projects/trendz/te0803/vivado_lab
  TE::BOARDDEF_PATH:        C:/Projects/trendz/te0803/board_files
  TE::FIRMWARE_PATH:        C:/Projects/trendz/te0803/firmware
  TE::IP_PATH:              C:/Projects/trendz/te0803/ip_lib
  TE::BD_PATH:              C:/Projects/trendz/te0803/block_design
  TE::XDC_PATH:             C:/Projects/trendz/te0803/constraints
  TE::HDL_PATH:             C:/Projects/trendz/te0803/hdl
  TE::SET_PATH:             C:/Projects/trendz/te0803/settings
  TE::WORKSPACE_HSI_PATH:   C:/Projects/trendz/te0803/workspace/hsi
  TE::WORKSPACE_SDK_PATH:   C:/Projects/trendz/te0803/workspace/sdk
  TE::LIB_PATH:             C:/Projects/trendz/te0803/sw_lib
  TE::SCRIPT_PATH:          C:/Projects/trendz/te0803/scripts
  TE::DOC_PATH:             C:/Projects/trendz/te0803/doc
  TE::PREBUILT_BI_PATH:     C:/Projects/trendz/te0803/prebuilt/boot_images
  TE::PREBUILT_HW_PATH:     C:/Projects/trendz/te0803/prebuilt/hardware
  TE::PREBUILT_SW_PATH:     C:/Projects/trendz/te0803/prebuilt/software
  TE::PREBUILT_OS_PATH:     C:/Projects/trendz/te0803/prebuilt/os
  TE::LOG_PATH:             C:/Projects/trendz/te0803/v_log
  TE::BACKUP_PATH:          C:/Projects/trendz/te0803/backup
  TE::ZIP_PATH:             C:/Program Files/7-Zip/7z.exe
  TE::SDSOC_PATH:           C:/Projects/trendz/te0803/../SDSoC_PFM
  TE::TMP_PATH:             C:/Projects/trendz/te0803/tmp
  TE::XILINXGIT_DEVICETREE: B:/xilinx_git/device-tree-xlnx
  TE::XILINXGIT_UBOOT:       
  TE::XILINXGIT_LINUX:       
  ------
INFO: [TE_INIT-16] Read board part definition list (File C:/Projects/trendz/te0803/board_files/TE0803_board_files.csv).
INFO: [TE_INIT-18] Read Software list (File: C:/Projects/trendz/te0803/sw_lib/apps_list.csv).
INFO: [TE_INIT-22] Read ZIP ignore list (File: C:/Projects/trendz/te0803/sw_lib/apps_list.csv).
Found ID: 22
Board part csv name check:  22 is unique on position 0.
INFO: [TE_INIT-4] Board Part definition:
  TE::ID:             22
  TE::PRODID:         TE0803-01-04CG-1EA
  TE::PARTNAME:       xczu4cg-sfvc784-1-e
  TE::BOARDPART:      trenz.biz:te0803_4cg_1e_tebf0808:part0:2.0
  TE::SHORTDIR:       4cg_sk
  TE::ZYNQFLASHTYP:   qspi_dual_parallel
  TE::FPGAFLASHTYP:   mt25qu512-qspi-x8-dual_parallel
  ------
Generate new project (Path: C:/Projects/trendz/te0803/vivado).
INFO: [TE_INIT-69] Set Board Definition path: C:/Projects/trendz/te0803/board_files
INFO: [TE_INIT-70] Set IP path : C:/Projects/trendz/te0803/ip_lib
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/Projects/trendz/te0803/ip_lib'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2017.4/data/ip'.
Start import design
INFO: [TE_UTIL-8] Following xdc files were found:
   C:/Projects/trendz/te0803/constraints/vivado_target.xdc
 C:/Projects/trendz/te0803/constraints/_i_bitgen.xdc
  ------
Set processing order normal for C:/Projects/trendz/te0803/constraints/vivado_target.xdc
Set use for synthesis and implementation for C:/Projects/trendz/te0803/constraints/vivado_target.xdc
Set processing order normal for C:/Projects/trendz/te0803/constraints/_i_bitgen.xdc
Set use for implementation only for C:/Projects/trendz/te0803/constraints/_i_bitgen.xdc
INFO: [TE_UTIL-2] Following block designs were found:
   C:/Projects/trendz/te0803/block_design/zusys_bd.tcl
  ------
INFO: [TE_INIT-8] Found BD-Design:
  TE::BD_TCLNAME:       zusys_bd
  TE::PR_TOPLEVELNAME: zusys_wrapper
  ------
  TE::IS_ZUSYS:        true
INFO: [TE_UTIL-2] Following block designs were found:
   C:/Projects/trendz/te0803/block_design/zusys_bd.tcl
  ------
INFO: [TE_BD-0] This block design tcl-file was generate with Trenz Electronic GmbH Board Part:trenz.biz:te0803_es1:part0:1.0, FPGA: xczu3eg-sfvc784-1-i-es1 at 2018-01-15T14:15:21.
INFO: [TE_BD-1] This block design tcl-file was modified by TE-Scripts. Modifications are labelled with comment tag  # #TE_MOD# on the Block-Design tcl-file.
INFO: [BD_TCL-3] Currently there is no design <zusys> in project, so creating one...
Wrote  : <C:/Projects/trendz/te0803/vivado/te0803.srcs/sources_1/bd/zusys/zusys.bd>
INFO: [BD_TCL-4] Making design <zusys> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "zusys".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: 
xilinx.com:ip:zynq_ultra_ps_e:3.1  .
INFO: [PSU-1]  DP_AUDIO clock source: RPLL is also being used by other peripheral clocks. Their outputs may get impacted if any driver changes DP_AUDIO PLL source to support runtime audio change
Wrote  : <C:/Projects/trendz/te0803/vivado/te0803.srcs/sources_1/bd/zusys/zusys.bd>
Adding cell -- xilinx.com:ip:zynq_ultra_ps_e:3.1 - zynq_ultra_ps_e_0
Successfully read diagram <zusys> from BD file <C:/Projects/trendz/te0803/vivado/te0803.srcs/sources_1/bd/zusys/zusys.bd>
ERROR: [BD 41-758] The following clock pins are not connected to a valid clock source:
/zynq_ultra_ps_e_0/dp_s_axis_audio_clk

ERROR: [TE_INIT-146] Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR: (TE_INIT-146) Script (TE::VIV::import_design) failed: ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.
.
ERROR:(TE) Script (TE::INIT::run_project) failed: .
ERROR:(TE) Script (TE::main) failed: .
INFO: [Common 17-206] Exiting Vivado at Thu Apr 12 12:53:30 2018...
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JH

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #5 on: April 13, 2018, 02:34:34 PM »
Hi,

Quote

I'm getting a similar error myself running on Vivado 2017.4

Based on vivado example: TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip
Your ZIP time stamp is very strange.
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-RevisionHistory
You has:                20180411081757
But I've put online: 20180411082116

Block Design, you used has also other timestamp than this one in the newer version. Can you download again please.

This different version is very strange, but don't matter. Can you please try again with the newer version please.

br
John
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gordonk

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #6 on: April 13, 2018, 06:26:15 PM »
Quote from: JH on April 13, 2018, 02:34:34 PM
Hi,
Your ZIP time stamp is very strange.
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-RevisionHistory
You has:                20180411081757
But I've put online: 20180411082116

Block Design, you used has also other timestamp than this one in the newer version. Can you download again please.

This different version is very strange, but don't matter. Can you please try again with the newer version please.

br
John

Hi John,

Thank you for prompt reply.

I downloaded the reference design here  (test_board):
http://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0803/Reference_Design/2017.4/test_board/TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip

I tried the one you referenced (StarterKit) and it worked.
https://wiki.trenz-electronic.de/display/PD/TE0803+StarterKit#TE0803StarterKit-RevisionHistory

StarterKit - TE0803 StarterKit Linux Design
test_board - TE0803 Simple Board Design

I was hoping to use the Simple Board Design to start as we are not using Linux.

-Gordon
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JH

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #7 on: April 13, 2018, 07:11:10 PM »
Hi,
sorry, OK test_board design my mistake.

But see:
https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-DesignFlow
See step 4 create project --> Important: Use Board Part Files, which did not ends with *_tebf0808

Test_board Design is for minimal setup(Module only). Starterkit is for TEBF0808. We provide 2 board part files, one with the minimum setup and one with the basic setup for TEBF0808.
You can use Starterkit design also without linux. Linux is optional. It's only a example. You can also modify PS settings, there are much more options possible, than this basic settings, this depends on the usage.

br
John
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gordonk

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Re: TEBE0808 2016.4 Vivado script_main.tcl error
« Reply #8 on: April 13, 2018, 07:14:41 PM »
Quote from: JH on April 13, 2018, 07:11:10 PM
Hi,
sorry, OK test_board design my mistake.

But see:
https://wiki.trenz-electronic.de/display/PD/TE0803+Test+Board#TE0803TestBoard-DesignFlow
See step 4 create project --> Important: Use Board Part Files, which did not ends with *_tebf0808

Test_board Design is for minimal setup(Module only). Starterkit is for TEBF0808. We provide 2 board part files, one with the minimum setup and one with the basic setup for TEBF0808.
You can use Starterkit design also without linux. Linux is optional. It's only a example. You can also modify PS settings, there are much more options possible, than this basic settings, this depends on the usage.

br
John

I see. Thanks John!
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