ISE 14.6 & DDR3 & TE0600

[alexsandr-ter]

I added mig 3.6 and created config for dd3, after map I saw error:
   ERROR:Place:864 - Incompatible IOB's are locked to the same bank 3
   Conflicting IO Standards are:
   IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = 12
   List of locked IOB's:
      mcb3_dram_dq<0>
      mcb3_dram_dq<1>
      mcb3_dram_dq<2>
      mcb3_dram_dq<3>
      mcb3_dram_dq<4>
      mcb3_dram_dq<5>
      mcb3_dram_dq<6>
      mcb3_dram_dq<7>
I had next constaints:
############################################################################
## Memory Controller 3                               
## Memory Device: DDR3_SDRAM->MT41J128M16XX-187E
## Frequency: 333.333 MHz
## Time Period: 3000 ps
## Supported Part Numbers: MT41J128M16HA-187E
############################################################################
NET sys_clk LOC = AA12 | IOSTANDARD = LVCMOS33;
NET sys_clk TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 8 ns HIGH 50%;

INST "u_ddr3_mem/memc3_infrastructure_inst/u_pll_adv" LOC = "PLL_ADV_X0Y2";

#CONFIG VCCAUX=2.5; # Valid values are 2.5 and 3.3

#CONFIG MCB_PERFORMANCE= EXTENDED;
###########################################################################
## Clock constraints                                                       
############################################################################
#NET "memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
#TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3"  8  ns HIGH 50 %;
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
################# Адресная шина ##########################################
#NET  "mcb3_dram_a[0]"    LOC = "H2" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[1]"    LOC = "H1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[2]"    LOC = "H5" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[3]"    LOC = "K6" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[4]"    LOC = "F3" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[5]"    LOC = "K3" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[6]"    LOC = "J4" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[7]"    LOC = "H6" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[8]"    LOC = "E3" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[9]"    LOC = "E1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[10]"   LOC = "G4" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[11]"   LOC = "C1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[12]"   LOC = "D1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_a[13]"   LOC = "G6" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
################ Шина выбора банка ##########################################
#NET  "mcb3_dram_ba[0]"   LOC = "G3" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_ba[1]"   LOC = "G1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_ba[2]"   LOC = "F1" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
################ Шина данных ################################################
#NET  "mcb3_dram_dq[0]"   LOC = "N3" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[1]"   LOC = "N1" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[2]"   LOC = "M2" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[3]"   LOC = "M1" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[4]"   LOC = "J3" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[5]"   LOC = "J1" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[6]"   LOC = "K2" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_dq[7]"   LOC = "K1" | IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
####
#NET  "mcb3_dram_ck"      LOC = "H4" | IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_ck_n"    LOC = "H3" | IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50;
NET  "mcb3_dram_dqs"     LOC = "L3" | IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
NET  "mcb3_dram_dqs_n"   LOC = "L1" | IOSTANDARD = DIFF_SSTL15_II  | OUT_TERM = UNTUNED_50 | IN_TERM = NONE;
#NET  "mcb3_dram_cke"     LOC = "D2" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_dm"      LOC = "L4" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_odt"     LOC = "J6" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_ras_n"   LOC = "K5" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_cas_n"   LOC = "K4" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_dram_reset_n" LOC = "C3" | IOSTANDARD = LVCMOS15;
#NET  "mcb3_dram_we_n"    LOC = "F2" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;
#NET  "mcb3_rzq"          LOC = "K7" | IOSTANDARD = SSTL15_II  | OUT_TERM = UNTUNED_50;

How I can correct this mistake?

[Oleksandr Kiyenko]

Hello Alexander
You probably make mistake during UCF creation.
At first glance I see that IOSTANDARD is not correct. Looks like you have some mix between files created by coregen and your files.
Please see our reference projects
https://github.com/Trenz-Electronic/TE060X-GigaBee-Reference-Designs/tree/master/GigaBee_ISE12.4-MIG

Best regards
Oleksandr Kiyenko