hi alex,
sry maybe my goal was not clear because of big post ;-)
yes I want to sent every 50µs a 4 bytes long package, filled with data from adc, but for testing I implemented just an easy counter, to see if all the packages are arriving in textfile
I was looking for PKTEND signal and noticed that its already right implemented in fx2_core (by the way I'm using v1_50_a), and it works with smaller packages, so I don't have to do something with PKTEND signal?!
I begin to despair, because it won't work on hardware, but in simulation. I always receive different results and loosing data.
Tried to change clocks, packetlenghts, timeout, but no success.
Here is my very minimum vhdl example, its just the fx2 core and a process with generating data every 50µs.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:21:36 03/29/2012
-- Design Name:
-- Module Name: system - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
--use IEEE.numeric_std.ALL; --für to_std_logic
use IEEE.NUMERIC_STD.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
Library UNISIM;
use UNISIM.vcomponents.all;
entity system is
generic( --hold gibt an wie lange ein sample impuls gehalten wird
t_sample_max1119 : integer := 50000/10; --achtung: doppelte zeit pro kanal (größe in ns)
t_sample_max1119_hold : integer := 200/10
);
port (
SYS_Clk_pin : in std_logic;
SYS_Rst_pin : in std_logic;
-- ChipScope : out std_logic_vector(0 to 31) := (others => '0');
--LED
fpga_0_LED_GPIO_d_out_pin : out std_logic := '0';
--USB Controller
USB_IFCLK_pin : in std_logic;
USB_SLRD_pin : out std_logic;
USB_SLWR_pin : out std_logic;
USB_FLAGA_pin : in std_logic;
USB_FLAGB_pin : in std_logic;
USB_FLAGC_pin : in std_logic;
USB_FLAGD_pin : in std_logic;
USB_SLOE_pin : out std_logic;
USB_PKTEND_pin : out std_logic:='0';
USB_FIFOADR_pin : out std_logic_vector(1 downto 0); --"00"=EP2,"01"=EP4,"10"=EP6,11"=EP8
USB_FD_pin : inout std_logic_vector(7 downto 0) := (others => 'Z')
);
end system;
architecture Behavioral of system is
signal SYS_Clk : std_logic;
signal USB_FD_T : std_logic_vector(7 downto 0);
signal USB_FD_O : std_logic_vector(7 downto 0);
signal USB_FD_I : std_logic_vector(7 downto 0);
signal Reg_in_0 : std_logic_vector(0 to 31) := (others => '0');
signal Reg_in_1 : std_logic_vector(0 to 31) := (others => '0');
signal Reg_out_0 : std_logic_vector(0 to 31);
signal TX_FIFO_Clk : std_logic := '0';
signal RX_FIFO_Clk : std_logic := '0';
signal USB_RX_Clk : std_logic := '0';
--commands
constant sample : std_logic_vector(0 to 3) := X"1";
constant set_chan : std_logic_vector(0 to 3) := X"2";
constant set_led : std_logic_vector(0 to 3) := X"F";
-- 0x1 --> sample
signal sample_en : std_logic := '0';
signal sample_en_temp : std_logic := '0'; --sample_en flank detection
-- 0x2 --> aktivate chanels
signal chan_en : std_logic_vector(0 to 3) := (others => '0'); -- jedes bit steht für einen adc bzw. eine adc gruppe (max1119_A, max11628, ads8326, max1119_B)
COMPONENT dcm
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKDV_OUT : OUT std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
COMPONENT fx2_core
PORT(
SYS_Clk : IN std_logic;
SYS_Rst : IN std_logic;
Reg_in_0 : IN std_logic_vector(0 to 31);
Reg_in_1 : IN std_logic_vector(0 to 31);
USB_RX_CLK : IN std_logic;
USB_IFCLK : IN std_logic;
USB_FLAGA : IN std_logic;
USB_FLAGB : IN std_logic;
USB_FLAGC : IN std_logic;
USB_FLAGD : IN std_logic;
USB_FD_I : IN std_logic_vector(7 downto 0);
TX_FIFO_Clk : IN std_logic;
RX_FIFO_Clk : IN std_logic;
TX_FIFO_DIN : IN std_logic_vector(0 to 31);
TX_FIFO_VLD : IN std_logic;
RX_FIFO_RDY : IN std_logic;
Reg_out_0 : OUT std_logic_vector(0 to 31);
Interrupt : OUT std_logic_vector(0 to 7);
USB_SLRD : OUT std_logic;
USB_SLWR : OUT std_logic;
USB_SLOE : OUT std_logic;
USB_PKTEND : OUT std_logic;
USB_FIFOADR : OUT std_logic_vector(1 downto 0);
USB_FD_T : OUT std_logic_vector(7 downto 0);
USB_FD_O : OUT std_logic_vector(7 downto 0);
TX_FIFO_RDY : OUT std_logic;
RX_FIFO_DOUT : OUT std_logic_vector(0 to 31);
RX_FIFO_VLD : OUT std_logic;
ChipScope : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--fifos
signal FIFO_IN_din : std_logic_vector(0 to 31) := (others => '-');
signal FIFO_IN_ready : std_logic;
signal FIFO_IN_valid : std_logic := '0';
signal FIFO_OUT_dout : std_logic_vector(0 to 31) := (others => '0');
signal FIFO_OUT_ready : std_logic := '0';
signal FIFO_OUT_valid : std_logic;
--max1119-A
signal cnt4max1119_A : integer range 0 to 65536 := 0;
signal cnt_max1119_A_packages : std_logic_vector(0 to 8) := (others => '0'); --package counter
signal cnt_max1119_A_packages_temp : std_logic_vector(0 to 8) := (others => '0'); --flankdetection
signal detect3 : std_logic := '0'; --package generation valid
signal FIFO_OUT_valid_temp : std_logic := '0'; --for FIFO_OUT_valid flank detection
begin
TX_FIFO_Clk <= SYS_Clk; --100 Mhz
RX_FIFO_Clk <= SYS_Clk; --100 Mhz
USB_RX_Clk <= USB_IFCLK_pin; --48 Mhz
Inst_dcm: dcm PORT MAP(
CLKIN_IN => SYS_Clk_pin,
RST_IN => SYS_Rst_pin,
CLKDV_OUT => open,
CLKFX_OUT => SYS_Clk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => open
);
inst_fx2_core: fx2_core PORT MAP(
SYS_Clk => SYS_Clk,
SYS_Rst => SYS_Rst_pin,
Reg_in_0 => Reg_in_0,
Reg_in_1 =>Reg_in_1,
Reg_out_0 => Reg_out_0,
Interrupt => open,
USB_RX_CLK => USB_RX_CLK,
USB_IFCLK => USB_IFCLK_pin,
USB_SLRD => USB_SLRD_pin,
USB_SLWR => USB_SLWR_pin,
USB_FLAGA => '0',
USB_FLAGB => USB_FLAGB_pin,
USB_FLAGC => USB_FLAGC_pin,
USB_FLAGD => USB_FLAGD_pin,
USB_SLOE => USB_SLOE_pin,
USB_PKTEND => USB_PKTEND_pin,
USB_FIFOADR => USB_FIFOADR_pin,
USB_FD_T => USB_FD_T,
USB_FD_O => USB_FD_O,
USB_FD_I => USB_FD_I,
TX_FIFO_Clk => TX_FIFO_Clk,
RX_FIFO_Clk => RX_FIFO_Clk,
TX_FIFO_DIN => FIFO_IN_din,
TX_FIFO_VLD => FIFO_IN_valid,
TX_FIFO_RDY => FIFO_IN_ready,
RX_FIFO_DOUT => FIFO_OUT_dout,
RX_FIFO_VLD => FIFO_OUT_valid,
RX_FIFO_RDY => FIFO_OUT_ready,
ChipScope => open
);
bidirectional_bus:
for i in 0 to 7 generate
begin
IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer,
-- "0"-"12"
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register,
-- "AUTO", "0"-"6"
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => USB_FD_I(i), -- Buffer output
IO => USB_FD_pin(i), -- Buffer inout port (connect directly to top-level port)
I => USB_FD_O(i), -- Buffer input
T => USB_FD_T(i) -- 3-state enable input, high=input, low=output
);
end generate;
--Endpoint 6
Reg_in_0(26 to 27) <= "10";
Reg_in_1(26 to 27) <= "10";
--sample_en flank detection
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1') then
sample_en_temp <= sample_en;
end if;
end process;
--max1119_A sample process (every 50us cnt_max1119_A_packages increases --> generate a package)
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1') then
if(sample_en = '1' and chan_en(0) = '1') then
if(cnt4max1119_A < t_sample_max1119-1 and sample_en_temp = '1') then
cnt4max1119_A <= cnt4max1119_A + 1;
else
if(cnt_max1119_A_packages = "111111111") then --overflow
cnt_max1119_A_packages <= (others => '0');
else
cnt_max1119_A_packages <= cnt_max1119_A_packages + 1;
end if;
cnt4max1119_A <= 0;
end if;
else
cnt4max1119_A <= 0;
cnt_max1119_A_packages <= (others => '0');
end if;
end if;
end process;
--generate packages
process(SYS_Clk)
begin
if(SYS_Clk'event and SYS_Clk = '1' and sample_en = '1') then
cnt_max1119_A_packages_temp <= cnt_max1119_A_packages;
if(cnt_max1119_A_packages /= cnt_max1119_A_packages_temp and chan_en(0) = '1') then
detect3 <= '1';
end if;
if(detect3 = '1' and USB_FLAGB_pin = '0') then
FIFO_IN_valid <= '1';
--4 byte package
FIFO_IN_din <= "00001" & "01" & cnt_max1119_A_packages & X"00" & "10010011";
detect3 <= '0';
else
FIFO_IN_valid <= '0';
end if;
end if;
end process;
--process for receiving and interpreting external commands
observe_usb_input: process(USB_IFCLK_pin)
begin
if(USB_IFCLK_pin'event and USB_IFCLK_pin = '1') then
FIFO_OUT_valid_temp <= FIFO_OUT_valid;
if(USB_FLAGD_pin = '0') then --rx fifo isn't empty
FIFO_OUT_ready <= '1';
else
FIFO_OUT_ready <= '0';
end if;
if(FIFO_OUT_valid = '1' and FIFO_OUT_valid_temp ='0') then --rising edge
--interpret received data
case(FIFO_OUT_dout(0 to 3)) is
when sample =>
sample_en <= FIFO_OUT_dout(4);
fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);
when set_chan =>
chan_en(0 to 3) <= FIFO_OUT_dout(4 to 7);
when set_LED =>
fpga_0_LED_GPIO_d_out_pin <= FIFO_OUT_dout(4);
when others => null; --no knowing command
end case;
end if;
end if;
end process;
end Behavioral;
with TX_PACKET_LEN = 4 and packets=10 I expect
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 03 00 93"
4. "0A 04 00 93"
5. "0A 05 00 93"
6. "0A 06 00 93"
7. "0A 07 00 93"
8. "0A 08 00 93"
9. "0A 09 00 93"
10. "0A 0A 00 93"
but there are 3 different types of results I get
first: datatransfer with less errors (of TE0300_GetData) than packets
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 03 00 93"
4. "0A 08 00 93"
5. "0A 0A 00 93"
6. "CD CD CD CD" (error: 31)
7. "CD CD CD CD" (error: 995)
8. "CD CD CD CD" (error: 995)
9. "CD CD CD CD" (error: 995)
10. "CD CD CD CD" (error: 995)
second: datatransfer with no errors
1. "0A 01 00 93"
2. "0A 02 00 93"
3. "0A 05 00 93"
4. "0A 0A 00 93"
5. "0A 0F 00 93"
6. "0A 14 00 93"
7. "0A 19 00 93"
8. "0A 1E 00 93"
9. "0A 23 00 93"
10. "0A 22 00 93"
and third: datatransfer completely failed
10 times error: 995 occurs
conspicuous is beside the indeterministic behaviour, that if data is transferred, some of the packets are lost
do you maybe have got a minimum example or something like that? I really don't know how to solve this problem :-(
